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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 09:38:55 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-01 09:38:55 -0700 |
| commit | e8a2d10982cd8f6ba3b0e66fbd922b051073f0cf (patch) | |
| tree | 7fa627b9a520a09ff6e61df2596f29849f6c7db3 /techlibs | |
| parent | acd8bc0a7496c69864a7dd032eb7f4db7e2e1f2d (diff) | |
| parent | 66806085db7d730c27a330e541f8aecbba3bd342 (diff) | |
| download | yosys-e8a2d10982cd8f6ba3b0e66fbd922b051073f0cf.tar.gz yosys-e8a2d10982cd8f6ba3b0e66fbd922b051073f0cf.tar.bz2 yosys-e8a2d10982cd8f6ba3b0e66fbd922b051073f0cf.zip | |
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/xc6s_brams_map.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/xc6s_brams_map.v b/techlibs/xilinx/xc6s_brams_map.v index c9b33af42..16fd15e74 100644 --- a/techlibs/xilinx/xc6s_brams_map.v +++ b/techlibs/xilinx/xc6s_brams_map.v @@ -52,7 +52,7 @@ module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT .CLKBRDCLK(CLK2 ^ !CLKPOL2), .ENBRDEN(A1EN), .REGCEBREGCE(|1), - .RSTB(|0) + .RSTBRST(|0) ); endmodule @@ -217,7 +217,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT .CLKBRDCLK(CLK3 ^ !CLKPOL3), .ENBRDEN(|1), .REGCEBREGCE(|0), - .RSTB(|0), + .RSTBRST(|0), .WEBWEU(B1EN_2) ); end else begin @@ -248,7 +248,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT .CLKBRDCLK(CLK3 ^ !CLKPOL3), .ENBRDEN(|1), .REGCEBREGCE(|0), - .RSTB(|0), + .RSTBRST(|0), .WEBWEU(B1EN_2) ); end endgenerate |