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| author | Clifford Wolf <clifford@clifford.at> | 2013-06-10 13:19:04 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-06-10 13:19:04 +0200 |
| commit | db98a18edb02a5c3a0c3f26efec0e01f8232790a (patch) | |
| tree | 2f1d2758fe775d7d39b0a09561525681f9c6452f /techlibs | |
| parent | af79b4bd9827ec0c8aff284a44e861ab0d0efff1 (diff) | |
| download | yosys-db98a18edb02a5c3a0c3f26efec0e01f8232790a.tar.gz yosys-db98a18edb02a5c3a0c3f26efec0e01f8232790a.tar.bz2 yosys-db98a18edb02a5c3a0c3f26efec0e01f8232790a.zip | |
Enabled AST/Verilog front-end optimizations per default
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions