diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 17:09:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 17:09:17 -0700 |
| commit | d386177e6d99ea2b3ef4b798653c0b1d7786e6b8 (patch) | |
| tree | e9c2c3bb1ceefe06e71346d61e69d52ff4375388 /techlibs | |
| parent | 3ef927647c04bccce1d72751f6fb95ac4ac7e98b (diff) | |
| download | yosys-d386177e6d99ea2b3ef4b798653c0b1d7786e6b8.tar.gz yosys-d386177e6d99ea2b3ef4b798653c0b1d7786e6b8.tar.bz2 yosys-d386177e6d99ea2b3ef4b798653c0b1d7786e6b8.zip | |
ABC doesn't like negative delays in flop boxes...
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_xc7.box | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 73f532711..f59cdcde8 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -65,29 +65,29 @@ $__ABC_ASYNC 1000 0 2 1 # Inputs: C CE D R \$pastQ # Outputs: Q FDRE 1001 1 5 1 -- 109 -46 358 0 +0 109 0 358 0 # Inputs: C CE D R \$pastQ # Outputs: Q FDRE_1 1002 1 5 1 -- 109 -46 358 0 +0 109 0 358 0 # Inputs: C CE CLR D \$pastQ # Outputs: Q FDCE 1003 1 5 1 -- 109 - -46 0 +0 109 764 0 0 # Inputs: C CE CLR D \$pastQ # Outputs: Q FDCE_1 1004 1 5 1 -- 109 - -46 0 +0 109 764 0 0 # Inputs: C CE D PRE \$pastQ # Outputs: Q FDPE 1005 1 5 1 -- 109 -46 - 0 +0 109 0 764 0 # Inputs: C CE D PRE \$pastQ # Outputs: Q FDPE_1 1006 1 5 1 -- 109 -46 - 0 +0 109 0 764 0 |