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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 18:16:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 18:16:14 -0700 |
| commit | c2f3f116d041b97b0d8b6ed28c87810bf6c2630e (patch) | |
| tree | 94ad1bb4bf0e203cad1b43c6950cab3d49b49652 /techlibs | |
| parent | c04921c3a8391d2335fab42ef354bb2bb2f3ac2a (diff) | |
| download | yosys-c2f3f116d041b97b0d8b6ed28c87810bf6c2630e.tar.gz yosys-c2f3f116d041b97b0d8b6ed28c87810bf6c2630e.tar.bz2 yosys-c2f3f116d041b97b0d8b6ed28c87810bf6c2630e.zip | |
Use $__ABC_FF_ instead of $_FF_
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/ff_map.v | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v index 1f0635614..bfd4c6998 100644 --- a/techlibs/xilinx/ff_map.v +++ b/techlibs/xilinx/ff_map.v @@ -29,12 +29,20 @@ module \$_DFF_P_ (input D, C, output Q); `else wire Q_next; \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0)); - \$_FF_ abc_dff (.D(Q_next), .Q(Q)); + \$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q)); `endif endmodule module \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule -module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule +module \$_DFFE_PP_ (input D, C, E, output Q); +`ifndef _ABC + FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); +`else + wire Q_next; + \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(E), .R(1'b0)); + \$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q)); +`endif +endmodule module \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule module \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule |