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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 14:21:10 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-25 14:21:10 -0700 |
| commit | a7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4 (patch) | |
| tree | 7ad89229bedd897e3dc895084a99197dcf04b8a3 /techlibs | |
| parent | 59b355fb85cb7cda4a25696850bb3caffce3115f (diff) | |
| parent | 08221edbc15333bcd05ae65cee09c86f875076ab (diff) | |
| download | yosys-a7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4.tar.gz yosys-a7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4.tar.bz2 yosys-a7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4.zip | |
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
xilinx: tidy up cells_sim.v a little
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index d87cfe91b..f5850d8a2 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -3387,10 +3387,10 @@ module DSP48E1 ( reg signed [24:0] Dr; reg signed [17:0] Br1, Br2; reg signed [47:0] Cr; - reg [4:0] INMODEr = 5'b0; - reg [6:0] OPMODEr = 7'b0; - reg [3:0] ALUMODEr = 4'b0; - reg [2:0] CARRYINSELr = 3'b0; + reg [4:0] INMODEr; + reg [6:0] OPMODEr; + reg [3:0] ALUMODEr; + reg [2:0] CARRYINSELr; generate // Configurable A register @@ -3572,11 +3572,13 @@ module DSP48E1 ( // Carry in wire A24_xnor_B17d = A_MULT[24] ~^ B_MULT[17]; - reg CARRYINr = 1'b0, A24_xnor_B17 = 1'b0; + reg CARRYINr, A24_xnor_B17; generate + if (CARRYINREG == 1) initial CARRYINr = 1'b0; if (CARRYINREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) CARRYINr <= 1'b0; else if (CECARRYIN) CARRYINr <= CARRYIN; end else always @* CARRYINr = CARRYIN; + if (MREG == 1) initial A24_xnor_B17 = 1'b0; if (MREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) A24_xnor_B17 <= 1'b0; else if (CEM) A24_xnor_B17 <= A24_xnor_B17d; end else always @* A24_xnor_B17 = A24_xnor_B17d; endgenerate |