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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-06 15:18:18 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-06 15:18:18 +0200 |
| commit | a4b59de5d48a89ba5e1b46eb44877a91ceb6fa44 (patch) | |
| tree | e94e14733c13e234d5c5055082d732be26fd6d9b /techlibs | |
| parent | 44a9dcbbbf47f1a6f524c6328ff775f29573a935 (diff) | |
| parent | 023086bd46bc828621ebb171b159efe1398aaecf (diff) | |
| download | yosys-a4b59de5d48a89ba5e1b46eb44877a91ceb6fa44.tar.gz yosys-a4b59de5d48a89ba5e1b46eb44877a91ceb6fa44.tar.bz2 yosys-a4b59de5d48a89ba5e1b46eb44877a91ceb6fa44.zip | |
Merge pull request #1251 from YosysHQ/clifford/nmux
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simcells.v | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 289673e82..64720e598 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -230,6 +230,25 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- +//- $_NMUX_ (A, B, S, Y) +//- +//- A 2-input inverting MUX gate. +//- +//- Truth table: A B S | Y +//- -------+--- +//- 0 - 0 | 1 +//- 1 - 0 | 0 +//- - 0 1 | 1 +//- - 1 1 | 0 +//- +module \$_NMUX_ (A, B, S, Y); +input A, B, S; +output Y; +assign Y = S ? !B : !A; +endmodule + +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- //- $_MUX4_ (A, B, C, D, S, T, Y) //- //- A 4-input MUX gate. |