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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-11-07 13:15:57 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-11-07 13:15:57 +0100 |
| commit | 96df99dafa5a175200036015030c3427758b872c (patch) | |
| tree | 24d29901f2ccb9f16fe7198c0ce28a046b3b1fb1 /techlibs | |
| parent | bc0e69f5c85fe5a2c6bd5d51acdb5b9be4e61d95 (diff) | |
| parent | a4eb7e41c08d6efa02e00dee16674dfb68c9cacc (diff) | |
| download | yosys-96df99dafa5a175200036015030c3427758b872c.tar.gz yosys-96df99dafa5a175200036015030c3427758b872c.tar.bz2 yosys-96df99dafa5a175200036015030c3427758b872c.zip | |
Merge pull request #3536 from YosysHQ/claire/vcdend
Add extra time at the end of a sat VCD trace
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions