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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 15:13:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 15:13:05 -0700 |
| commit | 8a86f9bb6259d335a250868c6f060936a482be8a (patch) | |
| tree | a10bebfb9c082da77563aa045b5d1288ecd7c621 /techlibs | |
| parent | d80678e581899315791706ee1703bf700b0f9c15 (diff) | |
| download | yosys-8a86f9bb6259d335a250868c6f060936a482be8a.tar.gz yosys-8a86f9bb6259d335a250868c6f060936a482be8a.tar.bz2 yosys-8a86f9bb6259d335a250868c6f060936a482be8a.zip | |
Add box delays for FD*
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_xc7.box | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 9aef37545..4caf69320 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -44,19 +44,19 @@ RAM128X1D 5 0 17 2 # Inputs: C CE D R \$pastQ # Outputs: Q FDRE 6 1 5 1 -- - - - - +- 109 -46 358 0 -# Inputs: C CE D S +# Inputs: C CE D S \$pastQ # Outputs: Q -FDSE 7 0 4 1 -- - - - +FDSE 7 0 5 1 +- 109 -46 358 0 -# Inputs: C CE CLR D +# Inputs: C CE CLR D \$pastQ # Outputs: Q -FDCE 8 0 4 1 -- - - - +FDCE 8 0 5 1 +- 109 - -46 0 -# Inputs: C CE D PRE +# Inputs: C CE D PRE \$pastQ # Outputs: Q -FDPE 9 0 4 1 -- - - - +FDPE 9 0 5 1 +- 109 -46 - 0 |