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| author | Stefan Biereigel <stefan@biereigel.de> | 2019-05-27 19:07:46 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-27 19:07:46 +0200 |
| commit | 816082d5a11e758b6ff68a2dc442fc2519356669 (patch) | |
| tree | 6b32d20e36c18af97076ca77f0c7d36fd7b25d53 /techlibs | |
| parent | f68b658b4b88b9a71377d19d7d693f07eccf433e (diff) | |
| parent | 92dde319fc603223304a64a5a49bbbe6c1ec3045 (diff) | |
| download | yosys-816082d5a11e758b6ff68a2dc442fc2519356669.tar.gz yosys-816082d5a11e758b6ff68a2dc442fc2519356669.tar.bz2 yosys-816082d5a11e758b6ff68a2dc442fc2519356669.zip | |
Merge branch 'master' into wandwor
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/drams.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt index e6635d0e2..91632bcee 100644 --- a/techlibs/xilinx/drams.txt +++ b/techlibs/xilinx/drams.txt @@ -26,11 +26,15 @@ bram $__XILINX_RAM128X1D endbram match $__XILINX_RAM64X1D + min bits 5 + min wports 1 make_outreg or_next_if_better endmatch match $__XILINX_RAM128X1D + min bits 9 + min wports 1 make_outreg endmatch |