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authorMiodrag Milanović <mmicko@gmail.com>2019-10-18 10:53:56 +0200
committerGitHub <noreply@github.com>2019-10-18 10:53:56 +0200
commit66fca65b58bfb944cad45da5836613726498e4b7 (patch)
treea78b5d92952ea9f95623bb3daf8028d2402d023b /techlibs
parent46af9a0ff7727c2d47b1dc12501e3328cba1f2e9 (diff)
parent5ffb0053ec7d53ffc5c57e3277bfbab5d3fddb54 (diff)
downloadyosys-66fca65b58bfb944cad45da5836613726498e4b7.tar.gz
yosys-66fca65b58bfb944cad45da5836613726498e4b7.tar.bz2
yosys-66fca65b58bfb944cad45da5836613726498e4b7.zip
Merge branch 'master' into mmicko/anlogic
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/ecp5/Makefile.inc12
-rw-r--r--techlibs/ecp5/abc9_5g.box (renamed from techlibs/ecp5/abc_5g.box)2
-rw-r--r--techlibs/ecp5/abc9_5g.lut (renamed from techlibs/ecp5/abc_5g.lut)0
-rw-r--r--techlibs/ecp5/abc9_5g_nowide.lut (renamed from techlibs/ecp5/abc_5g_nowide.lut)0
-rw-r--r--techlibs/ecp5/abc9_map.v (renamed from techlibs/ecp5/abc_map.v)2
-rw-r--r--techlibs/ecp5/abc9_model.v5
-rw-r--r--techlibs/ecp5/abc9_unmap.v (renamed from techlibs/ecp5/abc_unmap.v)2
-rw-r--r--techlibs/ecp5/abc_model.v5
-rw-r--r--techlibs/ecp5/cells_bb.v7
-rw-r--r--techlibs/ecp5/cells_ff.vh16
-rw-r--r--techlibs/ecp5/cells_sim.v12
-rw-r--r--techlibs/ecp5/synth_ecp5.cc10
-rw-r--r--techlibs/ice40/Makefile.inc13
-rw-r--r--techlibs/ice40/abc9_hx.box (renamed from techlibs/ice40/abc_hx.box)0
-rw-r--r--techlibs/ice40/abc9_hx.lut (renamed from techlibs/ice40/abc_hx.lut)0
-rw-r--r--techlibs/ice40/abc9_lp.box (renamed from techlibs/ice40/abc_lp.box)0
-rw-r--r--techlibs/ice40/abc9_lp.lut (renamed from techlibs/ice40/abc_lp.lut)0
-rw-r--r--techlibs/ice40/abc9_model.v27
-rw-r--r--techlibs/ice40/abc9_u.box (renamed from techlibs/ice40/abc_u.box)0
-rw-r--r--techlibs/ice40/abc9_u.lut (renamed from techlibs/ice40/abc_u.lut)0
-rw-r--r--techlibs/ice40/cells_sim.v185
-rw-r--r--techlibs/ice40/synth_ice40.cc5
-rw-r--r--techlibs/xilinx/Makefile.inc12
-rw-r--r--techlibs/xilinx/abc9_map.v (renamed from techlibs/xilinx/abc_map.v)66
-rw-r--r--techlibs/xilinx/abc9_model.v (renamed from techlibs/xilinx/abc_model.v)40
-rw-r--r--techlibs/xilinx/abc9_unmap.v (renamed from techlibs/xilinx/abc_unmap.v)14
-rw-r--r--techlibs/xilinx/abc9_xc7.box (renamed from techlibs/xilinx/abc_xc7.box)24
-rw-r--r--techlibs/xilinx/abc9_xc7.lut (renamed from techlibs/xilinx/abc_xc7.lut)0
-rw-r--r--techlibs/xilinx/abc9_xc7_nowide.lut (renamed from techlibs/xilinx/abc_xc7_nowide.lut)0
-rw-r--r--techlibs/xilinx/cells_sim.v49
-rw-r--r--techlibs/xilinx/cells_xtra.py10
-rw-r--r--techlibs/xilinx/synth_xilinx.cc31
-rw-r--r--techlibs/xilinx/xc6s_brams_bb.v8
-rw-r--r--techlibs/xilinx/xc6s_cells_xtra.v10
-rw-r--r--techlibs/xilinx/xc6v_cells_xtra.v98
-rw-r--r--techlibs/xilinx/xc7_brams_bb.v16
-rw-r--r--techlibs/xilinx/xc7_cells_xtra.v98
37 files changed, 305 insertions, 474 deletions
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index b03da164c..5832d07ee 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -15,12 +15,12 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.box))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.lut))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g_nowide.lut))
EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
.SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc9_5g.box
index a336b4a85..2bc945a54 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc9_5g.box
@@ -18,7 +18,7 @@ CCU2C 1 1 9 3
# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
# Outputs: DO0, DO1, DO2, DO3
# name ID w/b ins outs
-$__ABC_DPR16X4_COMB 2 0 8 4
+$__ABC9_DPR16X4_COMB 2 0 8 4
#A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3
0 0 0 0 141 379 275 379
diff --git a/techlibs/ecp5/abc_5g.lut b/techlibs/ecp5/abc9_5g.lut
index e8aa9b35d..e8aa9b35d 100644
--- a/techlibs/ecp5/abc_5g.lut
+++ b/techlibs/ecp5/abc9_5g.lut
diff --git a/techlibs/ecp5/abc_5g_nowide.lut b/techlibs/ecp5/abc9_5g_nowide.lut
index 60352d892..60352d892 100644
--- a/techlibs/ecp5/abc_5g_nowide.lut
+++ b/techlibs/ecp5/abc9_5g_nowide.lut
diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc9_map.v
index ffd25f06d..d8d70f9f6 100644
--- a/techlibs/ecp5/abc_map.v
+++ b/techlibs/ecp5/abc9_map.v
@@ -20,5 +20,5 @@ module TRELLIS_DPR16X4 (
.RAD(RAD), .DO(\$DO )
);
- \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
+ \$__ABC9_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
endmodule
diff --git a/techlibs/ecp5/abc9_model.v b/techlibs/ecp5/abc9_model.v
new file mode 100644
index 000000000..1dc8b5617
--- /dev/null
+++ b/techlibs/ecp5/abc9_model.v
@@ -0,0 +1,5 @@
+// ---------------------------------------
+
+(* abc9_box_id=2 *)
+module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+endmodule
diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc9_unmap.v
index d43cdd93f..9ae143c46 100644
--- a/techlibs/ecp5/abc_unmap.v
+++ b/techlibs/ecp5/abc9_unmap.v
@@ -1,5 +1,5 @@
// ---------------------------------------
-module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
assign Y = A;
endmodule
diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
deleted file mode 100644
index 56a733b75..000000000
--- a/techlibs/ecp5/abc_model.v
+++ /dev/null
@@ -1,5 +0,0 @@
-// ---------------------------------------
-
-(* abc_box_id=2 *)
-module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
-endmodule
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 0a5046db2..ae124e7a3 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -334,6 +334,13 @@ module ECLKSYNCB(
endmodule
(* blackbox *)
+module ECLKBRIDGECS(
+ input CLK0, CLK1, SEL,
+ output ECSOUT
+);
+endmodule
+
+(* blackbox *)
module DCCA(
input CLKI, CE,
output CLKO
diff --git a/techlibs/ecp5/cells_ff.vh b/techlibs/ecp5/cells_ff.vh
index 0c9689ebd..501c1b3b2 100644
--- a/techlibs/ecp5/cells_ff.vh
+++ b/techlibs/ecp5/cells_ff.vh
@@ -23,15 +23,15 @@ module FD1S3JX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLI
// module FL1S3AY(); endmodule
// Diamond I/O registers
-module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
// TODO: Diamond I/O latches
// module IFS1S1B(input PD, D, SCLK, output Q); endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index db77dc127..f467218cc 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -9,19 +9,19 @@ module LUT4(input A, B, C, D, output Z);
endmodule
// ---------------------------------------
-(* abc_box_id=4, lib_whitebox *)
+(* abc9_box_id=4, lib_whitebox *)
module L6MUX21 (input D0, D1, SD, output Z);
assign Z = SD ? D1 : D0;
endmodule
// ---------------------------------------
-(* abc_box_id=1, lib_whitebox *)
+(* abc9_box_id=1, lib_whitebox *)
module CCU2C(
- (* abc_carry *)
+ (* abc9_carry *)
input CIN,
input A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1,
- (* abc_carry *)
+ (* abc9_carry *)
output COUT
);
parameter [15:0] INIT0 = 16'h0000;
@@ -103,7 +103,7 @@ module TRELLIS_RAM16X2 (
endmodule
// ---------------------------------------
-(* abc_box_id=3, lib_whitebox *)
+(* abc9_box_id=3, lib_whitebox *)
module PFUMX (input ALUT, BLUT, C0, output Z);
assign Z = C0 ? ALUT : BLUT;
endmodule
@@ -115,7 +115,7 @@ module TRELLIS_DPR16X4 (
input WRE,
input WCK,
input [3:0] RAD,
- /* (* abc_arrival=<TODO> *) */
+ /* (* abc9_arrival=<TODO> *) */
output [3:0] DO
);
parameter WCKMUX = "WCK";
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 1f5b1cb6b..a79dee31f 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -297,6 +297,7 @@ struct SynthEcp5Pass : public ScriptPass
run("simplemap");
run("ecp5_ffinit");
run("ecp5_gsr");
+ run("attrmvcp -copy -attr syn_useioff");
run("opt_clean");
}
@@ -307,15 +308,16 @@ struct SynthEcp5Pass : public ScriptPass
}
std::string techmap_args = "-map +/ecp5/latches_map.v";
if (abc9)
- techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
+ techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1";
run("techmap " + techmap_args);
if (abc9) {
+ run("read_verilog -icells -lib +/ecp5/abc9_model.v");
if (nowidelut)
- run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
+ run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
else
- run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
- run("techmap -map +/ecp5/abc_unmap.v");
+ run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
+ run("techmap -map +/ecp5/abc9_unmap.v");
} else {
if (nowidelut)
run("abc -lut 4 -dress");
diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 92a9956ea..3c33fcb06 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,12 +28,13 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_model.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.lut))
$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc9_hx.box
index 3ea70bc91..3ea70bc91 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc9_hx.box
diff --git a/techlibs/ice40/abc_hx.lut b/techlibs/ice40/abc9_hx.lut
index 3b3bb11e2..3b3bb11e2 100644
--- a/techlibs/ice40/abc_hx.lut
+++ b/techlibs/ice40/abc9_hx.lut
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc9_lp.box
index 473e92fe9..473e92fe9 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc9_lp.box
diff --git a/techlibs/ice40/abc_lp.lut b/techlibs/ice40/abc9_lp.lut
index e72f760a2..e72f760a2 100644
--- a/techlibs/ice40/abc_lp.lut
+++ b/techlibs/ice40/abc9_lp.lut
diff --git a/techlibs/ice40/abc9_model.v b/techlibs/ice40/abc9_model.v
new file mode 100644
index 000000000..26cf6cc22
--- /dev/null
+++ b/techlibs/ice40/abc9_model.v
@@ -0,0 +1,27 @@
+(* abc9_box_id = 1, lib_whitebox *)
+module \$__ICE40_CARRY_WRAPPER (
+ (* abc9_carry *)
+ output CO,
+ output O,
+ input A, B,
+ (* abc9_carry *)
+ input CI,
+ input I0, I3
+);
+ parameter LUT = 0;
+ SB_CARRY carry (
+ .I0(A),
+ .I1(B),
+ .CI(CI),
+ .CO(CO)
+ );
+ SB_LUT4 #(
+ .LUT_INIT(LUT)
+ ) adder (
+ .I0(I0),
+ .I1(A),
+ .I2(B),
+ .I3(I3),
+ .O(O)
+ );
+endmodule
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc9_u.box
index f00e247b8..f00e247b8 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc9_u.box
diff --git a/techlibs/ice40/abc_u.lut b/techlibs/ice40/abc9_u.lut
index 1e4fcadb6..1e4fcadb6 100644
--- a/techlibs/ice40/abc_u.lut
+++ b/techlibs/ice40/abc9_u.lut
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 8e5e0358e..f9e79a61d 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2,9 +2,9 @@
`define SB_DFF_REG reg Q = 0
// `define SB_DFF_REG reg Q
-`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
-`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
-`define ABC_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc_arrival=TIME *) `endif
+`define ABC9_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc9_arrival=TIME *) `endif
+`define ABC9_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc9_arrival=TIME *) `endif
+`define ABC9_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc9_arrival=TIME *) `endif
// SiliconBlue IO Cells
@@ -145,34 +145,6 @@ module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
-(* abc_box_id = 1, lib_whitebox *)
-module \$__ICE40_CARRY_WRAPPER (
- (* abc_carry *)
- output CO,
- output O,
- input A, B,
- (* abc_carry *)
- input CI,
- input I0, I3
-);
- parameter LUT = 0;
- SB_CARRY carry (
- .I0(A),
- .I1(B),
- .CI(CI),
- .CO(CO)
- );
- SB_LUT4 #(
- .LUT_INIT(LUT)
- ) adder (
- .I0(I0),
- .I1(A),
- .I2(B),
- .I3(I3),
- .O(O)
- );
-endmodule
-
// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
@@ -180,9 +152,9 @@ endmodule
// Positive Edge SiliconBlue FF Cells
module SB_DFF (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, D
);
@@ -191,9 +163,9 @@ module SB_DFF (
endmodule
module SB_DFFE (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, E, D
);
@@ -203,9 +175,9 @@ module SB_DFFE (
endmodule
module SB_DFFSR (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, R, D
);
@@ -217,9 +189,9 @@ module SB_DFFSR (
endmodule
module SB_DFFR (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, R, D
);
@@ -231,9 +203,9 @@ module SB_DFFR (
endmodule
module SB_DFFSS (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, S, D
);
@@ -245,9 +217,9 @@ module SB_DFFSS (
endmodule
module SB_DFFS (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, S, D
);
@@ -259,9 +231,9 @@ module SB_DFFS (
endmodule
module SB_DFFESR (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, E, R, D
);
@@ -275,9 +247,9 @@ module SB_DFFESR (
endmodule
module SB_DFFER (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, E, R, D
);
@@ -289,9 +261,9 @@ module SB_DFFER (
endmodule
module SB_DFFESS (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, E, S, D
);
@@ -305,9 +277,9 @@ module SB_DFFESS (
endmodule
module SB_DFFES (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, E, S, D
);
@@ -321,9 +293,9 @@ endmodule
// Negative Edge SiliconBlue FF Cells
module SB_DFFN (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, D
);
@@ -332,9 +304,9 @@ module SB_DFFN (
endmodule
module SB_DFFNE (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, E, D
);
@@ -344,9 +316,9 @@ module SB_DFFNE (
endmodule
module SB_DFFNSR (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, R, D
);
@@ -358,9 +330,9 @@ module SB_DFFNSR (
endmodule
module SB_DFFNR (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, R, D
);
@@ -372,9 +344,9 @@ module SB_DFFNR (
endmodule
module SB_DFFNSS (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, S, D
);
@@ -386,9 +358,9 @@ module SB_DFFNSS (
endmodule
module SB_DFFNS (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, S, D
);
@@ -400,9 +372,9 @@ module SB_DFFNS (
endmodule
module SB_DFFNESR (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, E, R, D
);
@@ -416,9 +388,9 @@ module SB_DFFNESR (
endmodule
module SB_DFFNER (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, E, R, D
);
@@ -430,9 +402,9 @@ module SB_DFFNER (
endmodule
module SB_DFFNESS (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, E, S, D
);
@@ -446,9 +418,9 @@ module SB_DFFNESS (
endmodule
module SB_DFFNES (
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output `SB_DFF_REG,
input C, E, S, D
);
@@ -462,9 +434,9 @@ endmodule
// SiliconBlue RAM Cells
module SB_RAM40_4K (
- `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
- `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
- `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
+ `ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
@@ -633,9 +605,9 @@ module SB_RAM40_4K (
endmodule
module SB_RAM40_4KNR (
- `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
- `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
- `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
+ `ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
@@ -701,9 +673,9 @@ module SB_RAM40_4KNR (
endmodule
module SB_RAM40_4KNW (
- `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
- `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
- `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
+ `ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
@@ -769,9 +741,9 @@ module SB_RAM40_4KNW (
endmodule
module SB_RAM40_4KNRNW (
- `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
- `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
- `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
+ `ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
@@ -841,9 +813,9 @@ endmodule
module ICESTORM_LC (
input I0, I1, I2, I3, CIN, CLK, CEN, SR,
output LO,
- `ABC_ARRIVAL_HX(540)
- `ABC_ARRIVAL_LP(796)
- `ABC_ARRIVAL_U(1391)
+ `ABC9_ARRIVAL_HX(540)
+ `ABC9_ARRIVAL_LP(796)
+ `ABC9_ARRIVAL_U(1391)
output O,
output COUT
);
@@ -1445,7 +1417,6 @@ module SB_MAC16 (
input ADDSUBTOP, ADDSUBBOT,
input OHOLDTOP, OHOLDBOT,
input CI, ACCUMCI, SIGNEXTIN,
- //`ABC_ARRIVAL_U(1984) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [31:0] O,
output CO, ACCUMCO, SIGNEXTOUT
);
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 841f10244..b66c6bf57 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -245,7 +245,7 @@ struct SynthIce40Pass : public ScriptPass
define = "-D ICE40_U";
else
define = "-D ICE40_HX";
- run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
+ run("read_verilog " + define + " -lib +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}
@@ -349,6 +349,7 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc == "abc9") {
+ run("read_verilog -icells -lib +/ice40/abc9_model.v");
int wire_delay;
if (device_opt == "lp")
wire_delay = 400;
@@ -356,7 +357,7 @@ struct SynthIce40Pass : public ScriptPass
wire_delay = 750;
else
wire_delay = 250;
- run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+ run(abc + stringf(" -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
}
else
run(abc + " -dress -lut 4", "(skip if -noabc)");
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index ae82311a9..0ae67d9e7 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -44,12 +44,12 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_unmap.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_model.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7.box))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7.lut))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7_nowide.lut))
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc9_map.v
index e4976092c..0eac08f3f 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -39,8 +39,8 @@ module RAM32X1D (
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
);
- \$__ABC_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
- \$__ABC_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
+ \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
+ \$__ABC9_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
endmodule
module RAM64X1D (
@@ -62,8 +62,8 @@ module RAM64X1D (
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
);
- \$__ABC_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
- \$__ABC_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
+ \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
+ \$__ABC9_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
endmodule
module RAM128X1D (
@@ -84,8 +84,8 @@ module RAM128X1D (
.A(A),
.DPRA(DPRA)
);
- \$__ABC_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
- \$__ABC_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
+ \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
+ \$__ABC9_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
endmodule
module SRL16E (
@@ -101,7 +101,7 @@ module SRL16E (
.Q(\$Q ),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
);
- \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q));
+ \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q));
endmodule
module SRLC32E (
@@ -119,7 +119,7 @@ module SRLC32E (
.Q(\$Q ), .Q31(Q31),
.A(A), .CE(CE), .CLK(CLK), .D(D)
);
- \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
+ \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
endmodule
module DSP48E1 (
@@ -308,15 +308,15 @@ __CELL__ #(
if (AREG == 0 && MREG == 0 && PREG == 0)
assign iA = A, pA = 1'bx;
else
- \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
+ \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
if (BREG == 0 && MREG == 0 && PREG == 0)
assign iB = B, pB = 1'bx;
else
- \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
+ \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
if (CREG == 0 && PREG == 0)
assign iC = C, pC = 1'bx;
else
- \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
+ \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
if (DREG == 0)
assign iD = D;
else if (techmap_guard)
@@ -327,27 +327,27 @@ __CELL__ #(
assign pAD = 1'bx;
if (PREG == 0) begin
if (MREG == 1)
- \$__ABC_REG rM (.Q(pM));
+ \$__ABC9_REG rM (.Q(pM));
else
assign pM = 1'bx;
assign pP = 1'bx;
end else begin
assign pM = 1'bx;
- \$__ABC_REG rP (.Q(pP));
+ \$__ABC9_REG rP (.Q(pP));
end
if (MREG == 0 && PREG == 0)
assign mP = oP, mPCOUT = oPCOUT;
else
assign mP = 1'bx, mPCOUT = 1'bx;
- \$__ABC_DSP48E1_MULT_P_MUX muxP (
+ \$__ABC9_DSP48E1_MULT_P_MUX muxP (
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
);
- \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
+ \$__ABC9_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
);
- `DSP48E1_INST(\$__ABC_DSP48E1_MULT )
+ `DSP48E1_INST(\$__ABC9_DSP48E1_MULT )
end
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
// Disconnect the A-input if MREG is enabled, since
@@ -355,26 +355,26 @@ __CELL__ #(
if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
assign iA = A, pA = 1'bx;
else
- \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
+ \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
if (BREG == 0 && MREG == 0 && PREG == 0)
assign iB = B, pB = 1'bx;
else
- \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
+ \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
if (CREG == 0 && PREG == 0)
assign iC = C, pC = 1'bx;
else
- \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
+ \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
if (DREG == 0 && ADREG == 0)
assign iD = D, pD = 1'bx;
else
- \$__ABC_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
+ \$__ABC9_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
if (PREG == 0) begin
if (MREG == 1) begin
assign pAD = 1'bx;
- \$__ABC_REG rM (.Q(pM));
+ \$__ABC9_REG rM (.Q(pM));
end else begin
if (ADREG == 1)
- \$__ABC_REG rAD (.Q(pAD));
+ \$__ABC9_REG rAD (.Q(pAD));
else
assign pAD = 1'bx;
assign pM = 1'bx;
@@ -382,21 +382,21 @@ __CELL__ #(
assign pP = 1'bx;
end else begin
assign pAD = 1'bx, pM = 1'bx;
- \$__ABC_REG rP (.Q(pP));
+ \$__ABC9_REG rP (.Q(pP));
end
if (MREG == 0 && PREG == 0)
assign mP = oP, mPCOUT = oPCOUT;
else
assign mP = 1'bx, mPCOUT = 1'bx;
- \$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP (
+ \$__ABC9_DSP48E1_MULT_DPORT_P_MUX muxP (
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
);
- \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
+ \$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
);
- `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT )
+ `DSP48E1_INST(\$__ABC9_DSP48E1_MULT_DPORT )
end
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
// Disconnect the A-input if MREG is enabled, since
@@ -404,15 +404,15 @@ __CELL__ #(
if (AREG == 0 && PREG == 0)
assign iA = A, pA = 1'bx;
else
- \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
+ \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
if (BREG == 0 && PREG == 0)
assign iB = B, pB = 1'bx;
else
- \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
+ \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
if (CREG == 0 && PREG == 0)
assign iC = C, pC = 1'bx;
else
- \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
+ \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
if (DREG == 1 && techmap_guard)
$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
assign pD = 1'bx;
@@ -423,7 +423,7 @@ __CELL__ #(
$error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
assign pM = 1'bx;
if (PREG == 1)
- \$__ABC_REG rP (.Q(pP));
+ \$__ABC9_REG rP (.Q(pP));
else
assign pP = 1'bx;
@@ -431,14 +431,14 @@ __CELL__ #(
assign mP = oP, mPCOUT = oPCOUT;
else
assign mP = 1'bx, mPCOUT = 1'bx;
- \$__ABC_DSP48E1_P_MUX muxP (
+ \$__ABC9_DSP48E1_P_MUX muxP (
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
);
- \$__ABC_DSP48E1_PCOUT_MUX muxPCOUT (
+ \$__ABC9_DSP48E1_PCOUT_MUX muxPCOUT (
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
);
- `DSP48E1_INST(\$__ABC_DSP48E1 )
+ `DSP48E1_INST(\$__ABC9_DSP48E1 )
end
else
$error("Invalid DSP48E1 configuration");
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc9_model.v
index f19235a27..8c8e1556c 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -24,7 +24,7 @@
// Necessary to make these an atomic unit so that
// ABC cannot optimise just one of the MUXF7 away
// and expect to save on its delay
-(* abc_box_id = 3, lib_whitebox *)
+(* abc9_box_id = 3, lib_whitebox *)
module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
assign O = S1 ? (S0 ? I3 : I2)
: (S0 ? I1 : I0);
@@ -36,32 +36,32 @@ endmodule
// is only committed on the next clock edge).
// To model the combinatorial path, such cells have to be split
// into comb and seq parts, with this box modelling only the former.
-(* abc_box_id=2000 *)
-module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
+(* abc9_box_id=2000 *)
+module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
endmodule
// Box to emulate comb/seq behaviour of RAMD128
-(* abc_box_id=2001 *)
-module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
+(* abc9_box_id=2001 *)
+module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
endmodule
// Modules used to model the comb/seq behaviour of DSP48E1
-// With abc_map.v responsible for splicing the below modules
+// With abc9_map.v responsible for splicing the below modules
// between the combinatorial DSP48E1 box (e.g. disconnecting
// A when AREG, MREG or PREG is enabled and splicing in the
-// "$__ABC_DSP48E1_REG" blackbox as "REG" in the diagram below)
+// "$__ABC9_DSP48E1_REG" blackbox as "REG" in the diagram below)
// this acts to first disables the combinatorial path (as there
// is no connectivity through REG), and secondly, since this is
// blackbox a new PI will be introduced with an arrival time of
// zero.
-// Note: Since these "$__ABC_DSP48E1_REG" modules are of a
+// Note: Since these "$__ABC9_DSP48E1_REG" modules are of a
// sequential nature, they are not passed as a box to ABC and
// (desirably) represented as PO/PIs.
//
// At the DSP output, we place a blackbox mux ("M" in the diagram
// below) to capture the fact that the critical-path could come
// from any one of its inputs.
-// In contrast to "REG", the "$__ABC_DSP48E1_*_MUX" modules are
+// In contrast to "REG", the "$__ABC9_DSP48E1_*_MUX" modules are
// combinatorial blackboxes that do get passed to ABC.
// The propagation delay through this box (specified in the box
// file) captures the arrival time of the register (i.e.
@@ -90,18 +90,18 @@ endmodule
// B >>------| |
// +---------+
//
-`define ABC_DSP48E1_MUX(__NAME__) """
+`define ABC9_DSP48E1_MUX(__NAME__) """
module __NAME__ (input Aq, ADq, Bq, Cq, Dq, input [47:0] I, input Mq, input [47:0] P, input Pq, output [47:0] O);
endmodule
"""
-(* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX )
-(* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX )
-(* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX )
-(* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX )
-(* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX )
-(* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX )
+(* abc9_box_id=2100 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_P_MUX )
+(* abc9_box_id=2101 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_PCOUT_MUX )
+(* abc9_box_id=2102 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_P_MUX )
+(* abc9_box_id=2103 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX )
+(* abc9_box_id=2104 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_P_MUX )
+(* abc9_box_id=2105 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_PCOUT_MUX )
-`define ABC_DSP48E1(__NAME__) """
+`define ABC9_DSP48E1(__NAME__) """
module __NAME__ (
output [29:0] ACOUT,
output [17:0] BCOUT,
@@ -185,6 +185,6 @@ module __NAME__ (
parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
endmodule
"""
-(* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT )
-(* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT )
-(* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 )
+(* abc9_box_id=3000 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT )
+(* abc9_box_id=3001 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT_DPORT )
+(* abc9_box_id=3002 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1 )
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc9_unmap.v
index 8bd0579ed..ad6469702 100644
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc9_unmap.v
@@ -20,19 +20,19 @@
// ============================================================================
-module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
+module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
assign Y = A;
endmodule
-module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
+module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
assign Y = A;
endmodule
-module \$__ABC_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q);
+module \$__ABC9_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q);
parameter WIDTH = 1;
assign O = I;
endmodule
-(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *)
-module \$__ABC_DSP48E1_MUX (
+(* techmap_celltype = "$__ABC9_DSP48E1_MULT_P_MUX $__ABC9_DSP48E1_MULT_PCOUT_MUX $__ABC9_DSP48E1_MULT_DPORT_P_MUX $__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC9_DSP48E1_P_MUX $__ABC9_DSP48E1_PCOUT_MUX" *)
+module \$__ABC9_DSP48E1_MUX (
input Aq, Bq, Cq, Dq, ADq,
input [47:0] I,
input Mq,
@@ -43,8 +43,8 @@ module \$__ABC_DSP48E1_MUX (
assign O = I;
endmodule
-(* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT $__ABC_DSP48E1" *)
-module \$__ABC_DSP48E1 (
+(* techmap_celltype = "$__ABC9_DSP48E1_MULT $__ABC9_DSP48E1_MULT_DPORT $__ABC9_DSP48E1" *)
+module \$__ABC9_DSP48E1 (
(* techmap_autopurge *) output [29:0] ACOUT,
(* techmap_autopurge *) output [17:0] BCOUT,
(* techmap_autopurge *) output reg CARRYCASCOUT,
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 3da3d1b3f..774388d49 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -50,18 +50,18 @@ CARRY4 4 1 10 8
# into comb and seq parts, with this box modelling only the former.
# Inputs: A S0 S1 S2 S3 S4 S5
# Outputs: Y
-$__ABC_LUT6 2000 0 7 1
+$__ABC9_LUT6 2000 0 7 1
0 642 631 472 407 238 127
# SLICEM/A6LUT + F7BMUX
# Box to emulate comb/seq behaviour of RAMD128
# Inputs: A S0 S1 S2 S3 S4 S5 S6
# Outputs: DPO SPO
-$__ABC_LUT7 2001 0 8 1
+$__ABC9_LUT7 2001 0 8 1
0 1047 1036 877 812 643 532 478
# Boxes used to represent the comb/seq behaviour of DSP48E1
-# With abc_map.v responsible for disconnecting inputs to
+# With abc9_map.v responsible for disconnecting inputs to
# the combinatorial DSP48E1 model by a register (e.g.
# disconnecting A when AREG, MREG or PREG is enabled)
# this mux captures the existence of a replacement path
@@ -70,7 +70,7 @@ $__ABC_LUT7 2001 0 8 1
# the mux at zero time, the combinatorial delay through
# these muxes thus represents the clock-to-q delay at
# P/PCOUT.
-$__ABC_DSP48E1_MULT_P_MUX 2100 0 103 48
+$__ABC9_DSP48E1_MULT_P_MUX 2100 0 103 48
# A AD B C D I M P Pq
2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
@@ -120,7 +120,7 @@ $__ABC_DSP48E1_MULT_P_MUX 2100 0 103 48
2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-$__ABC_DSP48E1_MULT_PCOUT_MUX 2101 0 103 48
+$__ABC9_DSP48E1_MULT_PCOUT_MUX 2101 0 103 48
# A AD B C D I M P Pq
3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
@@ -170,7 +170,7 @@ $__ABC_DSP48E1_MULT_PCOUT_MUX 2101 0 103 48
3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
-$__ABC_DSP48E1_MULT_DPORT_P_MUX 2102 0 103 48
+$__ABC9_DSP48E1_MULT_DPORT_P_MUX 2102 0 103 48
# A AD B C D I M P Pq
3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
@@ -220,7 +220,7 @@ $__ABC_DSP48E1_MULT_DPORT_P_MUX 2102 0 103 48
3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX 2103 0 103 48
+$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX 2103 0 103 48
# A AD B C D I M P Pq
4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
@@ -270,7 +270,7 @@ $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX 2103 0 103 48
4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
-$__ABC_DSP48E1_P_MUX 2104 0 103 48
+$__ABC9_DSP48E1_P_MUX 2104 0 103 48
# A AD B C D I M P Pq
1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
@@ -320,7 +320,7 @@ $__ABC_DSP48E1_P_MUX 2104 0 103 48
1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-$__ABC_DSP48E1_PCOUT_MUX 2105 0 103 48
+$__ABC9_DSP48E1_PCOUT_MUX 2105 0 103 48
# A AD B C D I M P Pq
1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
@@ -371,7 +371,7 @@ $__ABC_DSP48E1_PCOUT_MUX 2105 0 103 48
1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
-$__ABC_DSP48E1_MULT 3000 0 263 154
+$__ABC9_DSP48E1_MULT 3000 0 263 154
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 -
@@ -635,7 +635,7 @@ $__ABC_DSP48E1_MULT 3000 0 263 154
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-$__ABC_DSP48E1_MULT_DPORT 3001 0 263 154
+$__ABC9_DSP48E1_MULT_DPORT 3001 0 263 154
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 -
@@ -899,7 +899,7 @@ $__ABC_DSP48E1_MULT_DPORT 3001 0 263 154
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-$__ABC_DSP48E1 3002 0 263 154
+$__ABC9_DSP48E1 3002 0 263 154
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 -
diff --git a/techlibs/xilinx/abc_xc7.lut b/techlibs/xilinx/abc9_xc7.lut
index bcbdec127..bcbdec127 100644
--- a/techlibs/xilinx/abc_xc7.lut
+++ b/techlibs/xilinx/abc9_xc7.lut
diff --git a/techlibs/xilinx/abc_xc7_nowide.lut b/techlibs/xilinx/abc9_xc7_nowide.lut
index fab48c879..fab48c879 100644
--- a/techlibs/xilinx/abc_xc7_nowide.lut
+++ b/techlibs/xilinx/abc9_xc7_nowide.lut
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 258999f18..03985b1be 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -38,6 +38,17 @@ module IBUF(
assign O = I;
endmodule
+module IBUFG(
+ output O,
+ (* iopad_external_pin *)
+ input I);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter IBUF_DELAY_VALUE = "0";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ assign O = I;
+endmodule
+
module OBUF(
(* iopad_external_pin *)
output O,
@@ -184,12 +195,12 @@ module MUXCY(output O, input CI, DI, S);
assign O = S ? CI : DI;
endmodule
-(* abc_box_id = 1, lib_whitebox *)
+(* abc9_box_id = 1, lib_whitebox *)
module MUXF7(output O, input I0, I1, S);
assign O = S ? I1 : I0;
endmodule
-(* abc_box_id = 2, lib_whitebox *)
+(* abc9_box_id = 2, lib_whitebox *)
module MUXF8(output O, input I0, I1, S);
assign O = S ? I1 : I0;
endmodule
@@ -198,12 +209,12 @@ module XORCY(output O, input CI, LI);
assign O = CI ^ LI;
endmodule
-(* abc_box_id = 4, lib_whitebox *)
+(* abc9_box_id = 4, lib_whitebox *)
module CARRY4(
- (* abc_carry *)
+ (* abc9_carry *)
output [3:0] CO,
output [3:0] O,
- (* abc_carry *)
+ (* abc9_carry *)
input CI,
input CYINIT,
input [3:0] DI, S
@@ -241,7 +252,7 @@ endmodule
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
module FDRE (
- (* abc_arrival=303 *)
+ (* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
@@ -264,7 +275,7 @@ module FDRE (
endmodule
module FDSE (
- (* abc_arrival=303 *)
+ (* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
@@ -287,7 +298,7 @@ module FDSE (
endmodule
module FDCE (
- (* abc_arrival=303 *)
+ (* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
@@ -312,7 +323,7 @@ module FDCE (
endmodule
module FDPE (
- (* abc_arrival=303 *)
+ (* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
@@ -337,7 +348,7 @@ module FDPE (
endmodule
module FDRE_1 (
- (* abc_arrival=303 *)
+ (* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
@@ -349,7 +360,7 @@ module FDRE_1 (
endmodule
module FDSE_1 (
- (* abc_arrival=303 *)
+ (* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
@@ -361,7 +372,7 @@ module FDSE_1 (
endmodule
module FDCE_1 (
- (* abc_arrival=303 *)
+ (* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
@@ -373,7 +384,7 @@ module FDCE_1 (
endmodule
module FDPE_1 (
- (* abc_arrival=303 *)
+ (* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
@@ -430,7 +441,7 @@ endmodule
module RAM32X1D (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
- (* abc_arrival=1153 *)
+ (* abc9_arrival=1153 *)
output DPO, SPO,
input D,
(* clkbuf_sink *)
@@ -453,7 +464,7 @@ endmodule
module RAM64X1D (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
- (* abc_arrival=1153 *)
+ (* abc9_arrival=1153 *)
output DPO, SPO,
input D,
(* clkbuf_sink *)
@@ -476,7 +487,7 @@ endmodule
module RAM128X1D (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
- (* abc_arrival=1153 *)
+ (* abc9_arrival=1153 *)
output DPO, SPO,
input D,
(* clkbuf_sink *)
@@ -496,7 +507,7 @@ endmodule
module SRL16E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
- (* abc_arrival=1472 *)
+ (* abc9_arrival=1472 *)
output Q,
input A0, A1, A2, A3, CE,
(* clkbuf_sink *)
@@ -544,9 +555,9 @@ endmodule
module SRLC32E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
- (* abc_arrival=1472 *)
+ (* abc9_arrival=1472 *)
output Q,
- (* abc_arrival=1114 *)
+ (* abc9_arrival=1114 *)
output Q31,
input [4:0] A,
input CE,
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index 13dbc0e14..9a4747ff3 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -53,7 +53,7 @@ XC6S_CELLS = [
# Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
- Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
+ # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
@@ -137,7 +137,7 @@ XC6V_CELLS = [
Cell('SYSMON'),
# Arithmetic functions.
- Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
+ #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
# Clock components.
# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
@@ -174,7 +174,7 @@ XC6V_CELLS = [
Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFDS_GTHE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
- Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
+ # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
@@ -264,7 +264,7 @@ XC7_CELLS = [
Cell('XADC'),
# Arithmetic functions.
- Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
+ #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
# Clock components.
# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
@@ -307,7 +307,7 @@ XC7_CELLS = [
Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
- Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
+ # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7085214de..f13740865 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -339,13 +339,17 @@ struct SynthXilinxPass : public ScriptPass
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
}
- if (check_label("map_dsp"), "(skip if '-nodsp')") {
+ if (check_label("map_dsp", "(skip if '-nodsp')")) {
if (!nodsp || help_mode) {
// NB: Xilinx multipliers are signed only
- run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 "
- "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
- "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
- "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
+ run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 "
+ "-D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " // Partial multipliers are intentionally
+ // limited to 18x18 in order to take
+ // advantage of the (PCOUT << 17) -> PCIN
+ // dedicated cascade chain capability
+ "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+ "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
+ "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
run("select a:mul2dsp");
run("setattr -unset mul2dsp");
run("opt_expr -fine");
@@ -474,13 +478,18 @@ struct SynthXilinxPass : public ScriptPass
run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
else if (abc9) {
if (family != "xc7")
- log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
- run("techmap -map +/xilinx/abc_map.v -max_iter 1");
- run("read_verilog -icells -lib +/xilinx/abc_model.v");
+ log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
+ "will use timing for 'xc7' instead.\n", family.c_str());
+ run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
+ run("read_verilog -icells -lib +/xilinx/abc9_model.v");
+ std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
+ abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
+ abc9_opts += " -nomfs";
if (nowidelut)
- run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
+ abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
else
- run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
+ abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
+ run("abc9" + abc9_opts);
}
else {
if (nowidelut)
@@ -498,7 +507,7 @@ struct SynthXilinxPass : public ScriptPass
if (help_mode)
techmap_args += " [-map " + ff_map_file + "]";
else if (abc9)
- techmap_args += " -map +/xilinx/abc_unmap.v";
+ techmap_args += " -map +/xilinx/abc9_unmap.v";
else
techmap_args += " -map " + ff_map_file;
run("techmap " + techmap_args);
diff --git a/techlibs/xilinx/xc6s_brams_bb.v b/techlibs/xilinx/xc6s_brams_bb.v
index 041d6b54f..3c323a90b 100644
--- a/techlibs/xilinx/xc6s_brams_bb.v
+++ b/techlibs/xilinx/xc6s_brams_bb.v
@@ -19,9 +19,13 @@ module RAMB8BWER (
input [1:0] WEAWEL,
input [1:0] WEBWEU,
+ /* (* abc9_arrival=<TODO> *) */
output [15:0] DOADO,
+ /* (* abc9_arrival=<TODO> *) */
output [15:0] DOBDO,
+ /* (* abc9_arrival=<TODO> *) */
output [1:0] DOPADOP,
+ /* (* abc9_arrival=<TODO> *) */
output [1:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@@ -109,9 +113,13 @@ module RAMB16BWER (
input [3:0] WEA,
input [3:0] WEB,
+ /* (* abc9_arrival=<TODO> *) */
output [31:0] DOA,
+ /* (* abc9_arrival=<TODO> *) */
output [31:0] DOB,
+ /* (* abc9_arrival=<TODO> *) */
output [3:0] DOPA,
+ /* (* abc9_arrival=<TODO> *) */
output [3:0] DOPB
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
diff --git a/techlibs/xilinx/xc6s_cells_xtra.v b/techlibs/xilinx/xc6s_cells_xtra.v
index f8dcce81d..7c0462b52 100644
--- a/techlibs/xilinx/xc6s_cells_xtra.v
+++ b/techlibs/xilinx/xc6s_cells_xtra.v
@@ -1282,16 +1282,6 @@ module IBUFDS_DIFF_OUT (...);
input IB;
endmodule
-module IBUFG (...);
- parameter CAPACITANCE = "DONT_CARE";
- parameter IBUF_DELAY_VALUE = "0";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- output O;
- (* iopad_external_pin *)
- input I;
-endmodule
-
module IBUFGDS (...);
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
diff --git a/techlibs/xilinx/xc6v_cells_xtra.v b/techlibs/xilinx/xc6v_cells_xtra.v
index b228e404d..87656fa49 100644
--- a/techlibs/xilinx/xc6v_cells_xtra.v
+++ b/techlibs/xilinx/xc6v_cells_xtra.v
@@ -647,94 +647,6 @@ module SYSMON (...);
input [6:0] DADDR;
endmodule
-module DSP48E1 (...);
- parameter integer ACASCREG = 1;
- parameter integer ADREG = 1;
- parameter integer ALUMODEREG = 1;
- parameter integer AREG = 1;
- parameter AUTORESET_PATDET = "NO_RESET";
- parameter A_INPUT = "DIRECT";
- parameter integer BCASCREG = 1;
- parameter integer BREG = 1;
- parameter B_INPUT = "DIRECT";
- parameter integer CARRYINREG = 1;
- parameter integer CARRYINSELREG = 1;
- parameter integer CREG = 1;
- parameter integer DREG = 1;
- parameter integer INMODEREG = 1;
- parameter integer MREG = 1;
- parameter integer OPMODEREG = 1;
- parameter integer PREG = 1;
- parameter SEL_MASK = "MASK";
- parameter SEL_PATTERN = "PATTERN";
- parameter USE_DPORT = "FALSE";
- parameter USE_MULT = "MULTIPLY";
- parameter USE_PATTERN_DETECT = "NO_PATDET";
- parameter USE_SIMD = "ONE48";
- parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
- parameter [47:0] PATTERN = 48'h000000000000;
- parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
- parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
- parameter [4:0] IS_INMODE_INVERTED = 5'b0;
- parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
- output [29:0] ACOUT;
- output [17:0] BCOUT;
- output CARRYCASCOUT;
- output [3:0] CARRYOUT;
- output MULTSIGNOUT;
- output OVERFLOW;
- output [47:0] P;
- output PATTERNBDETECT;
- output PATTERNDETECT;
- output [47:0] PCOUT;
- output UNDERFLOW;
- input [29:0] A;
- input [29:0] ACIN;
- (* invertible_pin = "IS_ALUMODE_INVERTED" *)
- input [3:0] ALUMODE;
- input [17:0] B;
- input [17:0] BCIN;
- input [47:0] C;
- input CARRYCASCIN;
- (* invertible_pin = "IS_CARRYIN_INVERTED" *)
- input CARRYIN;
- input [2:0] CARRYINSEL;
- input CEA1;
- input CEA2;
- input CEAD;
- input CEALUMODE;
- input CEB1;
- input CEB2;
- input CEC;
- input CECARRYIN;
- input CECTRL;
- input CED;
- input CEINMODE;
- input CEM;
- input CEP;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_CLK_INVERTED" *)
- input CLK;
- input [24:0] D;
- (* invertible_pin = "IS_INMODE_INVERTED" *)
- input [4:0] INMODE;
- input MULTSIGNIN;
- (* invertible_pin = "IS_OPMODE_INVERTED" *)
- input [6:0] OPMODE;
- input [47:0] PCIN;
- input RSTA;
- input RSTALLCARRYIN;
- input RSTALUMODE;
- input RSTB;
- input RSTC;
- input RSTCTRL;
- input RSTD;
- input RSTINMODE;
- input RSTM;
- input RSTP;
-endmodule
-
module BUFGCE (...);
parameter CE_TYPE = "SYNC";
parameter [0:0] IS_CE_INVERTED = 1'b0;
@@ -1909,16 +1821,6 @@ module IBUFDS_GTHE1 (...);
input IB;
endmodule
-module IBUFG (...);
- parameter CAPACITANCE = "DONT_CARE";
- parameter IBUF_DELAY_VALUE = "0";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- output O;
- (* iopad_external_pin *)
- input I;
-endmodule
-
module IBUFGDS (...);
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v
index a28ba5b14..c374f26b9 100644
--- a/techlibs/xilinx/xc7_brams_bb.v
+++ b/techlibs/xilinx/xc7_brams_bb.v
@@ -31,13 +31,13 @@ module RAMB18E1 (
input [1:0] WEA,
input [3:0] WEBWE,
- (* abc_arrival=2454 *)
+ (* abc9_arrival=2454 *)
output [15:0] DOADO,
- (* abc_arrival=2454 *)
+ (* abc9_arrival=2454 *)
output [15:0] DOBDO,
- (* abc_arrival=2454 *)
+ (* abc9_arrival=2454 *)
output [1:0] DOPADOP,
- (* abc_arrival=2454 *)
+ (* abc9_arrival=2454 *)
output [1:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@@ -169,13 +169,13 @@ module RAMB36E1 (
input [3:0] WEA,
input [7:0] WEBWE,
- (* abc_arrival=2454 *)
+ (* abc9_arrival=2454 *)
output [31:0] DOADO,
- (* abc_arrival=2454 *)
+ (* abc9_arrival=2454 *)
output [31:0] DOBDO,
- (* abc_arrival=2454 *)
+ (* abc9_arrival=2454 *)
output [3:0] DOPADOP,
- (* abc_arrival=2454 *)
+ (* abc9_arrival=2454 *)
output [3:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
diff --git a/techlibs/xilinx/xc7_cells_xtra.v b/techlibs/xilinx/xc7_cells_xtra.v
index 0d16f81c3..10eea4a5f 100644
--- a/techlibs/xilinx/xc7_cells_xtra.v
+++ b/techlibs/xilinx/xc7_cells_xtra.v
@@ -3376,94 +3376,6 @@ module XADC (...);
input [6:0] DADDR;
endmodule
-module DSP48E1 (...);
- parameter integer ACASCREG = 1;
- parameter integer ADREG = 1;
- parameter integer ALUMODEREG = 1;
- parameter integer AREG = 1;
- parameter AUTORESET_PATDET = "NO_RESET";
- parameter A_INPUT = "DIRECT";
- parameter integer BCASCREG = 1;
- parameter integer BREG = 1;
- parameter B_INPUT = "DIRECT";
- parameter integer CARRYINREG = 1;
- parameter integer CARRYINSELREG = 1;
- parameter integer CREG = 1;
- parameter integer DREG = 1;
- parameter integer INMODEREG = 1;
- parameter integer MREG = 1;
- parameter integer OPMODEREG = 1;
- parameter integer PREG = 1;
- parameter SEL_MASK = "MASK";
- parameter SEL_PATTERN = "PATTERN";
- parameter USE_DPORT = "FALSE";
- parameter USE_MULT = "MULTIPLY";
- parameter USE_PATTERN_DETECT = "NO_PATDET";
- parameter USE_SIMD = "ONE48";
- parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
- parameter [47:0] PATTERN = 48'h000000000000;
- parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
- parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
- parameter [4:0] IS_INMODE_INVERTED = 5'b0;
- parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
- output [29:0] ACOUT;
- output [17:0] BCOUT;
- output CARRYCASCOUT;
- output [3:0] CARRYOUT;
- output MULTSIGNOUT;
- output OVERFLOW;
- output [47:0] P;
- output PATTERNBDETECT;
- output PATTERNDETECT;
- output [47:0] PCOUT;
- output UNDERFLOW;
- input [29:0] A;
- input [29:0] ACIN;
- (* invertible_pin = "IS_ALUMODE_INVERTED" *)
- input [3:0] ALUMODE;
- input [17:0] B;
- input [17:0] BCIN;
- input [47:0] C;
- input CARRYCASCIN;
- (* invertible_pin = "IS_CARRYIN_INVERTED" *)
- input CARRYIN;
- input [2:0] CARRYINSEL;
- input CEA1;
- input CEA2;
- input CEAD;
- input CEALUMODE;
- input CEB1;
- input CEB2;
- input CEC;
- input CECARRYIN;
- input CECTRL;
- input CED;
- input CEINMODE;
- input CEM;
- input CEP;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_CLK_INVERTED" *)
- input CLK;
- input [24:0] D;
- (* invertible_pin = "IS_INMODE_INVERTED" *)
- input [4:0] INMODE;
- input MULTSIGNIN;
- (* invertible_pin = "IS_OPMODE_INVERTED" *)
- input [6:0] OPMODE;
- input [47:0] PCIN;
- input RSTA;
- input RSTALLCARRYIN;
- input RSTALUMODE;
- input RSTB;
- input RSTC;
- input RSTCTRL;
- input RSTD;
- input RSTINMODE;
- input RSTM;
- input RSTP;
-endmodule
-
module BUFGCE (...);
parameter CE_TYPE = "SYNC";
parameter [0:0] IS_CE_INVERTED = 1'b0;
@@ -4020,16 +3932,6 @@ module IBUFDS_INTERMDISABLE (...);
input INTERMDISABLE;
endmodule
-module IBUFG (...);
- parameter CAPACITANCE = "DONT_CARE";
- parameter IBUF_DELAY_VALUE = "0";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- output O;
- (* iopad_external_pin *)
- input I;
-endmodule
-
module IBUFGDS (...);
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 17:26:37 +0000