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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 11:50:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 11:50:14 -0700 |
| commit | 5466121ffb055c81946f8a729724febb8f93d4ef (patch) | |
| tree | 65d8e83b854b3d675776630aff8f935b7eac1bc6 /techlibs | |
| parent | ac5f3d500db46a4312d77f43fded2feb25545a3a (diff) | |
| download | yosys-5466121ffb055c81946f8a729724febb8f93d4ef.tar.gz yosys-5466121ffb055c81946f8a729724febb8f93d4ef.tar.bz2 yosys-5466121ffb055c81946f8a729724febb8f93d4ef.zip | |
Capture all data in one "abc_flop" attribute
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_ff.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v index 9f6f9c47e..a91720260 100644 --- a/techlibs/xilinx/abc_ff.v +++ b/techlibs/xilinx/abc_ff.v @@ -23,7 +23,7 @@ module \$__ABC_FF_ (input C, D, output Q); endmodule -(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *) +(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *) module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ ); parameter [0:0] INIT = 1'b0; //parameter [0:0] IS_C_INVERTED = 1'b0; |