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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 16:33:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 16:33:20 -0700 |
| commit | 1f722b35009275ad9a3f4ce4224fcb6973e3bc80 (patch) | |
| tree | 6c829c21dc2ebd31faaa81b4b7b59e216dd1fa01 /techlibs | |
| parent | 2c0be7aa5d7dcdf18678fb7b09ba1b3b5dd00998 (diff) | |
| download | yosys-1f722b35009275ad9a3f4ce4224fcb6973e3bc80.tar.gz yosys-1f722b35009275ad9a3f4ce4224fcb6973e3bc80.tar.bz2 yosys-1f722b35009275ad9a3f4ce4224fcb6973e3bc80.zip | |
Remove signed from ports in +/xilinx/dsp_map.v
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/dsp_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 423e12fbe..fdd55afe3 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -1,4 +1,4 @@ -module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed [42:0] Y); +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 0; |