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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-01 15:42:59 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-01 15:42:59 +0100 |
| commit | 1b159bc95528fd572443d6fb543b7e21bdbbf2a5 (patch) | |
| tree | 36f82ee840b757fbf9bfb2da59e93b19ac4fe7c7 /techlibs | |
| parent | 1df81f92ce171ba63cf0e4d10e6f203ca5f7f64e (diff) | |
| download | yosys-1b159bc95528fd572443d6fb543b7e21bdbbf2a5.tar.gz yosys-1b159bc95528fd572443d6fb543b7e21bdbbf2a5.tar.bz2 yosys-1b159bc95528fd572443d6fb543b7e21bdbbf2a5.zip | |
Added missing ports and parameters to xilinx brams
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/brams_map.v | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/techlibs/xilinx/brams_map.v b/techlibs/xilinx/brams_map.v index af057fe1f..2e9bba9a9 100644 --- a/techlibs/xilinx/brams_map.v +++ b/techlibs/xilinx/brams_map.v @@ -31,7 +31,8 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .IS_CLKARDCLK_INVERTED(!CLKPOL2), - .IS_CLKBWRCLK_INVERTED(!CLKPOL3) + .IS_CLKBWRCLK_INVERTED(!CLKPOL3), + .SIM_DEVICE("7SERIES") ) _TECHMAP_REPLACE_ ( .DOBDO(DO[63:32]), .DOADO(DO[31:0]), @@ -92,7 +93,8 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .IS_CLKARDCLK_INVERTED(!CLKPOL2), - .IS_CLKBWRCLK_INVERTED(!CLKPOL3) + .IS_CLKBWRCLK_INVERTED(!CLKPOL3), + .SIM_DEVICE("7SERIES") ) _TECHMAP_REPLACE_ ( .DOBDO(DO[31:16]), .DOADO(DO[15:0]), @@ -148,6 +150,9 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); wire [3:0] DIP, DOP; wire [31:0] DI, DO; + wire [31:0] DOBDO; + wire [3:0] DOPBDOP; + assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; @@ -160,7 +165,8 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .IS_CLKARDCLK_INVERTED(!CLKPOL2), - .IS_CLKBWRCLK_INVERTED(!CLKPOL3) + .IS_CLKBWRCLK_INVERTED(!CLKPOL3), + .SIM_DEVICE("7SERIES") ) _TECHMAP_REPLACE_ ( .DIADI(32'd0), .DIPADIP(4'd0), @@ -176,6 +182,8 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .DIBDI(DI), .DIPBDIP(DIP), + .DOBDO(DOBDO), + .DOPBDOP(DOPBDOP), .ADDRBWRADDR(B1ADDR_16), .CLKBWRCLK(CLK3), .ENBWREN(|1), @@ -213,6 +221,9 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); wire [1:0] DIP, DOP; wire [15:0] DI, DO; + wire [15:0] DOBDO; + wire [1:0] DOPBDOP; + assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; @@ -225,7 +236,8 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .IS_CLKARDCLK_INVERTED(!CLKPOL2), - .IS_CLKBWRCLK_INVERTED(!CLKPOL3) + .IS_CLKBWRCLK_INVERTED(!CLKPOL3), + .SIM_DEVICE("7SERIES") ) _TECHMAP_REPLACE_ ( .DIADI(16'b0), .DIPADIP(2'b0), @@ -241,6 +253,8 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .DIBDI(DI), .DIPBDIP(DIP), + .DOBDO(DOBDO), + .DOPBDOP(DOPBDOP), .ADDRBWRADDR(B1ADDR_14), .CLKBWRCLK(CLK3), .ENBWREN(|1), |