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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 08:06:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 08:06:16 -0700 |
| commit | e08df0c7390e1e7736c3d5b0abbe2679bf9b4518 (patch) | |
| tree | bbbcf14a457fded51a584780541c93dd888cc835 /techlibs/xilinx/synth_xilinx.cc | |
| parent | fc349de0338db3831e7156a5dc60f028382bcab1 (diff) | |
| download | yosys-e08df0c7390e1e7736c3d5b0abbe2679bf9b4518.tar.gz yosys-e08df0c7390e1e7736c3d5b0abbe2679bf9b4518.tar.bz2 yosys-e08df0c7390e1e7736c3d5b0abbe2679bf9b4518.zip | |
If init is 1'bx, do not add to dict as per @cliffordwolf
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
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