From 30854b9c7f23e2817a445761022668d6b0f7c0ef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 4 Feb 2020 15:35:47 +0100 Subject: xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. --- techlibs/xilinx/synth_xilinx.cc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 705591cf7..a7fa73837 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -438,7 +438,14 @@ struct SynthXilinxPass : public ScriptPass run("memory_bram -rules +/xilinx/{family}_brams.txt"); run("techmap -map +/xilinx/{family}_brams_map.v"); } else if (!nobram) { - if (family == "xc3sda") { + if (family == "xc2v" || family == "xc2vp" || family == "xc3s" || family == "xc3se") { + run("memory_bram -rules +/xilinx/xc2v_brams.txt"); + run("techmap -map +/xilinx/xc2v_brams_map.v"); + } else if (family == "xc3sa") { + // Superset of Virtex 2 primitives — uses common map file. + run("memory_bram -rules +/xilinx/xc3sa_brams.txt"); + run("techmap -map +/xilinx/xc2v_brams_map.v"); + } else if (family == "xc3sda") { // Supported block RAMs for Spartan 3A DSP are // a subset of Spartan 6's ones. run("memory_bram -rules +/xilinx/xc3sda_brams.txt"); -- cgit v1.2.3