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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-20 10:05:35 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-20 10:05:35 +0200 |
| commit | e3687f6f4e10789223213949b8490bd83ec285f2 (patch) | |
| tree | 3ed4f1885632a21a826582c947d41999be0e4987 /techlibs/xilinx/cells_xtra.v | |
| parent | eafc4bd49f3ff1e6a9e934aae065de183ca3a90e (diff) | |
| parent | 88be1cbfa50238d77d9489218a8cca7275731da9 (diff) | |
| download | yosys-e3687f6f4e10789223213949b8490bd83ec285f2.tar.gz yosys-e3687f6f4e10789223213949b8490bd83ec285f2.tar.bz2 yosys-e3687f6f4e10789223213949b8490bd83ec285f2.zip | |
Merge pull request #942 from YosysHQ/clifford/fix931
Improve proc full_case detection and handling
Diffstat (limited to 'techlibs/xilinx/cells_xtra.v')
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