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| author | Clifford Wolf <clifford@clifford.at> | 2018-11-12 09:09:22 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-11-12 09:09:22 +0100 |
| commit | dbc4cb8f4a39b2f9dd4ea8fb44196ce0a2905bbd (patch) | |
| tree | a815cfb68aced870a03e4ed7eeaf9a183b8b1f57 /techlibs/xilinx/cells_xtra.sh | |
| parent | 317cc9c2b7a68078fbcaf47caee66ad7cfe9fa8d (diff) | |
| parent | 99a14b0e37a383de39136807f9eb09e18fa859b9 (diff) | |
| download | yosys-dbc4cb8f4a39b2f9dd4ea8fb44196ce0a2905bbd.tar.gz yosys-dbc4cb8f4a39b2f9dd4ea8fb44196ce0a2905bbd.tar.bz2 yosys-dbc4cb8f4a39b2f9dd4ea8fb44196ce0a2905bbd.zip | |
Merge pull request #697 from eddiehung/xilinx_ps7
Add support for PS7 block for Xilinx
Diffstat (limited to 'techlibs/xilinx/cells_xtra.sh')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.sh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh index e7c7d17bf..0480410f5 100644 --- a/techlibs/xilinx/cells_xtra.sh +++ b/techlibs/xilinx/cells_xtra.sh @@ -112,6 +112,7 @@ function xtract_cell_decl() xtract_cell_decl PHY_CONTROL xtract_cell_decl PLLE2_ADV xtract_cell_decl PLLE2_BASE + xtract_cell_decl PS7 xtract_cell_decl PULLDOWN xtract_cell_decl PULLUP # xtract_cell_decl RAM128X1D |