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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-13 10:23:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-13 10:23:07 -0700 |
| commit | 0597a3ea238ee100607271fb25a2d09fbd128bf0 (patch) | |
| tree | 41b74055df055583d526755ea5a58db4268b7c02 /techlibs/xilinx/cells_sim.v | |
| parent | 2a1b98d478918b0a17c7e509ada6e7a71bbab526 (diff) | |
| download | yosys-0597a3ea238ee100607271fb25a2d09fbd128bf0.tar.gz yosys-0597a3ea238ee100607271fb25a2d09fbd128bf0.tar.bz2 yosys-0597a3ea238ee100607271fb25a2d09fbd128bf0.zip | |
Rename to XilinxDspPass
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
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