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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 13:50:19 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 13:50:19 -0700 |
| commit | b2b5cf78e21def63c54c080217d77afefba8e4c7 (patch) | |
| tree | 373a16624992c6e9da5a1696d1bca2f18892af29 /techlibs/xilinx/cells_sim.v | |
| parent | 6d9ba402632b1fd49e2c5ea63268682f126457c2 (diff) | |
| download | yosys-b2b5cf78e21def63c54c080217d77afefba8e4c7.tar.gz yosys-b2b5cf78e21def63c54c080217d77afefba8e4c7.tar.bz2 yosys-b2b5cf78e21def63c54c080217d77afefba8e4c7.zip | |
Rework muxcover decoder gen if more significant muxes are 1'bx
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
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