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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-13 10:23:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-13 10:23:07 -0700 |
| commit | 0597a3ea238ee100607271fb25a2d09fbd128bf0 (patch) | |
| tree | 41b74055df055583d526755ea5a58db4268b7c02 | |
| parent | 2a1b98d478918b0a17c7e509ada6e7a71bbab526 (diff) | |
| download | yosys-0597a3ea238ee100607271fb25a2d09fbd128bf0.tar.gz yosys-0597a3ea238ee100607271fb25a2d09fbd128bf0.tar.bz2 yosys-0597a3ea238ee100607271fb25a2d09fbd128bf0.zip | |
Rename to XilinxDspPass
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index cd88f9449..31c0d48c5 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -127,8 +127,8 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm) pm.blacklist(cell); } -struct Ice40DspPass : public Pass { - Ice40DspPass() : Pass("xilinx_dsp", "Xilinx: pack DSP registers") { } +struct XilinxDspPass : public Pass { + XilinxDspPass() : Pass("xilinx_dsp", "Xilinx: pack DSP registers") { } void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -156,6 +156,6 @@ struct Ice40DspPass : public Pass { for (auto module : design->selected_modules()) xilinx_dsp_pm(module, module->selected_cells()).run_xilinx_dsp(pack_xilinx_dsp); } -} Ice40DspPass; +} XilinxDspPass; PRIVATE_NAMESPACE_END |