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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-25 06:44:17 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-25 06:44:17 -0700 |
| commit | 5248a902ef9d2e30802c3924afb19a74935adbef (patch) | |
| tree | b4ec468e7a49d3c862e969514fa0bce1ca04bb63 /techlibs/intel_alm/common/dsp_sim.v | |
| parent | d6a289d3e3a09d1f11ec1588a4b4e9d6846517e8 (diff) | |
| parent | ab607e896e9f5faff939b4395b01344a36e9fc1b (diff) | |
| download | yosys-5248a902ef9d2e30802c3924afb19a74935adbef.tar.gz yosys-5248a902ef9d2e30802c3924afb19a74935adbef.tar.bz2 yosys-5248a902ef9d2e30802c3924afb19a74935adbef.zip | |
Merge pull request #1224 from YosysHQ/xilinx_fix_ff
xilinx: Fix missing cell name underscore in cells_map.v
Diffstat (limited to 'techlibs/intel_alm/common/dsp_sim.v')
0 files changed, 0 insertions, 0 deletions