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| author | Clifford Wolf <clifford@clifford.at> | 2020-01-02 19:57:27 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-02 19:57:27 +0100 |
| commit | ef6548203cca239a98b00ea652a92fe3e20f97d7 (patch) | |
| tree | de3501abee210bd05c710c0043e61ba92cbe54a8 /techlibs/intel | |
| parent | d6242be8021d126d7d0e6a96fc0140985fd4506f (diff) | |
| parent | 3edb2e708b09c7c9ead2aeb11e2be3cae88f8ee5 (diff) | |
| download | yosys-ef6548203cca239a98b00ea652a92fe3e20f97d7.tar.gz yosys-ef6548203cca239a98b00ea652a92fe3e20f97d7.tar.bz2 yosys-ef6548203cca239a98b00ea652a92fe3e20f97d7.zip | |
Merge pull request #1609 from YosysHQ/clifford/fix1596
Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs
Diffstat (limited to 'techlibs/intel')
0 files changed, 0 insertions, 0 deletions