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| author | Clifford Wolf <clifford@clifford.at> | 2020-01-02 18:58:45 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2020-01-02 18:58:45 +0100 |
| commit | 3edb2e708b09c7c9ead2aeb11e2be3cae88f8ee5 (patch) | |
| tree | c416b9941d3776f33bffb61e05f6e543cc8edf62 /techlibs/intel | |
| parent | 9e5ff30d0524629a1713d2e4cf92bbd9adffa857 (diff) | |
| download | yosys-3edb2e708b09c7c9ead2aeb11e2be3cae88f8ee5.tar.gz yosys-3edb2e708b09c7c9ead2aeb11e2be3cae88f8ee5.tar.bz2 yosys-3edb2e708b09c7c9ead2aeb11e2be3cae88f8ee5.zip | |
Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/intel')
0 files changed, 0 insertions, 0 deletions