From 2e37e62e6b926ca1712b1636ef720748e382dc97 Mon Sep 17 00:00:00 2001 From: Dan Ravensloft Date: Tue, 19 Nov 2019 10:19:00 +0000 Subject: synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6). --- techlibs/intel/Makefile.inc | 1 - 1 file changed, 1 deletion(-) (limited to 'techlibs/intel') diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index d97a9b58f..f751e341f 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -11,4 +11,3 @@ families := max10 arria10gx cyclonev cyclone10lp cycloneiv cycloneive $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v))) $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v))) #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v)) - -- cgit v1.2.3