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| author | whitequark <whitequark@whitequark.org> | 2018-12-07 19:14:07 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-01-02 13:12:17 +0000 |
| commit | efa278e232d20ea080743801bd91d55ec62955cf (patch) | |
| tree | 61971fdccdc1bb24169d78d0193eccc957232536 /techlibs/intel/cyclonev/cells_sim.v | |
| parent | 4b9f619349e6b7452739631635ab3b5a4d94b522 (diff) | |
| download | yosys-efa278e232d20ea080743801bd91d55ec62955cf.tar.gz yosys-efa278e232d20ea080743801bd91d55ec62955cf.tar.bz2 yosys-efa278e232d20ea080743801bd91d55ec62955cf.zip | |
Fix typographical and grammatical errors and inconsistencies.
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
Diffstat (limited to 'techlibs/intel/cyclonev/cells_sim.v')
| -rw-r--r-- | techlibs/intel/cyclonev/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/intel/cyclonev/cells_sim.v b/techlibs/intel/cyclonev/cells_sim.v index 5ecdabcfc..fa27c2c8e 100644 --- a/techlibs/intel/cyclonev/cells_sim.v +++ b/techlibs/intel/cyclonev/cells_sim.v @@ -54,7 +54,7 @@ module cyclonev_lcell_comb // Internal variables // Sub mask for fragmented LUTs wire [15:0] mask_a, mask_b, mask_c, mask_d; - // Independant output for fragmented LUTs + // Independent output for fragmented LUTs wire output_0, output_1, output_2, output_3; // Extended mode uses mux to define the output wire mux_0, mux_1; |