diff options
| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-10-04 17:01:30 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-05 16:23:49 +0200 |
| commit | 50bcd9a728ff89f220873b3345c4e18a65c4a37f (patch) | |
| tree | ff7b306d49b46ec25b7bfac26ca9ace82302a3f0 /techlibs/intel/a10gx/cells_map.v | |
| parent | fc3378916dbaf46018a99571ef190189088c225c (diff) | |
| download | yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.tar.gz yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.tar.bz2 yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.zip | |
Clean whitespace and permissions in techlibs/intel
Diffstat (limited to 'techlibs/intel/a10gx/cells_map.v')
| -rw-r--r--[-rwxr-xr-x] | techlibs/intel/a10gx/cells_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/intel/a10gx/cells_map.v b/techlibs/intel/a10gx/cells_map.v index 42e7926b8..1430e8551 100755..100644 --- a/techlibs/intel/a10gx/cells_map.v +++ b/techlibs/intel/a10gx/cells_map.v @@ -31,13 +31,13 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; input [WIDTH-1:0] A; - output Y; + output Y; generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function end else if (WIDTH == 2) begin - twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) + twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1)); end /*else if(WIDTH == 3) begin |