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author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-10-04 17:01:30 -0700 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-10-05 16:23:49 +0200 |
commit | 50bcd9a728ff89f220873b3345c4e18a65c4a37f (patch) | |
tree | ff7b306d49b46ec25b7bfac26ca9ace82302a3f0 /techlibs/intel/a10gx | |
parent | fc3378916dbaf46018a99571ef190189088c225c (diff) | |
download | yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.tar.gz yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.tar.bz2 yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.zip |
Clean whitespace and permissions in techlibs/intel
Diffstat (limited to 'techlibs/intel/a10gx')
-rw-r--r--[-rwxr-xr-x] | techlibs/intel/a10gx/cells_arith.v | 8 | ||||
-rw-r--r--[-rwxr-xr-x] | techlibs/intel/a10gx/cells_map.v | 4 | ||||
-rw-r--r--[-rwxr-xr-x] | techlibs/intel/a10gx/cells_sim.v | 2 |
3 files changed, 7 insertions, 7 deletions
diff --git a/techlibs/intel/a10gx/cells_arith.v b/techlibs/intel/a10gx/cells_arith.v index 470b686bb..89fb4561f 100755..100644 --- a/techlibs/intel/a10gx/cells_arith.v +++ b/techlibs/intel/a10gx/cells_arith.v @@ -45,10 +45,10 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); //wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH+1:0] C = {COx, CI}; - + /* Start implementation */ (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); - + genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice if(i==Y_WIDTH-1) begin @@ -61,5 +61,5 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); endgenerate /* End implementation */ assign X = AA ^ BB; - -endmodule + +endmodule diff --git a/techlibs/intel/a10gx/cells_map.v b/techlibs/intel/a10gx/cells_map.v index 42e7926b8..1430e8551 100755..100644 --- a/techlibs/intel/a10gx/cells_map.v +++ b/techlibs/intel/a10gx/cells_map.v @@ -31,13 +31,13 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; input [WIDTH-1:0] A; - output Y; + output Y; generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function end else if (WIDTH == 2) begin - twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) + twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1)); end /*else if(WIDTH == 3) begin diff --git a/techlibs/intel/a10gx/cells_sim.v b/techlibs/intel/a10gx/cells_sim.v index 1888682ef..e892b377e 100755..100644 --- a/techlibs/intel/a10gx/cells_sim.v +++ b/techlibs/intel/a10gx/cells_sim.v @@ -38,7 +38,7 @@ endmodule // twentynm_io_obuf /* Altera Arria 10 GX LUT Primitive */ module twentynm_lcell_comb (output combout, cout, sumout, - input dataa, datab, datac, datad, + input dataa, datab, datac, datad, input datae, dataf, datag, cin, input sharein); |