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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-25 17:23:48 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-07-25 17:23:48 +0200 |
| commit | eb663c75794d1249247ba88bf0bee835c98a8a85 (patch) | |
| tree | 8a3f1374d980bd05695e83a3f01a6d9a31f8fd48 /techlibs/intel/Makefile.inc | |
| parent | 5c933e511046d1720b74e47a6919c3f88ca8d303 (diff) | |
| parent | 67b4ce06e07fde80d5ac11cad4d673c501bdd421 (diff) | |
| download | yosys-eb663c75794d1249247ba88bf0bee835c98a8a85.tar.gz yosys-eb663c75794d1249247ba88bf0bee835c98a8a85.tar.bz2 yosys-eb663c75794d1249247ba88bf0bee835c98a8a85.zip | |
Merge branch 'ZirconiumX-synth_intel_m9k'
Diffstat (limited to 'techlibs/intel/Makefile.inc')
| -rw-r--r-- | techlibs/intel/Makefile.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index ec7cea379..7a3d2c71a 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -3,8 +3,8 @@ OBJS += techlibs/intel/synth_intel.o $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v)) $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v)) -$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams.txt)) -$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map.v)) +$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt)) +$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v)) $(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v)) $(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v)) $(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v)) |