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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-07 20:33:08 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 10:45:40 -0700 |
| commit | 9f3dc59ffe5f585a55ee5a9e4ab7781c3e600513 (patch) | |
| tree | 7b4e44e071110ebea6fba7013db08bc4ba23c34d /techlibs/greenpak4 | |
| parent | b049ead042f7453b806cf86c1103d3ec6bb8b616 (diff) | |
| download | yosys-9f3dc59ffe5f585a55ee5a9e4ab7781c3e600513.tar.gz yosys-9f3dc59ffe5f585a55ee5a9e4ab7781c3e600513.tar.bz2 yosys-9f3dc59ffe5f585a55ee5a9e4ab7781c3e600513.zip | |
Changed LEVEL resets to be edge triggered anyway
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index eb18a20b6..fc481975c 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -86,7 +86,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); end "LEVEL": begin - always @(posedge CLK or RST) begin + always @(posedge CLK or posedge RST) begin count <= count - 1'd1; if(count == 0) count <= COUNT_TO; @@ -204,7 +204,7 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, end "LEVEL": begin - always @(posedge CLK or RST) begin + always @(posedge CLK or posedge RST) begin //Main counter if(KEEP) begin @@ -339,7 +339,7 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, end "LEVEL": begin - always @(posedge CLK or RST) begin + always @(posedge CLK or posedge RST) begin //Main counter if(KEEP) begin @@ -439,7 +439,7 @@ module GP_COUNT8( end "LEVEL": begin - always @(posedge CLK or RST) begin + always @(posedge CLK or posedge RST) begin count <= count - 1'd1; if(count == 0) count <= COUNT_TO; |