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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-07 20:29:05 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 10:45:40 -0700 |
| commit | b049ead042f7453b806cf86c1103d3ec6bb8b616 (patch) | |
| tree | 2dfe3321484925bab032299ec38b946064f5ca47 /techlibs/greenpak4 | |
| parent | ac75524f69f193f8d1b49f8a891a29f90ca96799 (diff) | |
| download | yosys-b049ead042f7453b806cf86c1103d3ec6bb8b616.tar.gz yosys-b049ead042f7453b806cf86c1103d3ec6bb8b616.tar.bz2 yosys-b049ead042f7453b806cf86c1103d3ec6bb8b616.zip | |
Added level-triggered reset support to GP_COUNTx simulation models
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 70 |
1 files changed, 68 insertions, 2 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index 91d744039..eb18a20b6 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -86,6 +86,14 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); end "LEVEL": begin + always @(posedge CLK or RST) begin + count <= count - 1'd1; + if(count == 0) + count <= COUNT_TO; + + if(RST) + count <= 0; + end end default: begin @@ -178,7 +186,7 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; //Resets - if(RST) begin + if(!RST) begin if(RESET_VALUE == "ZERO") count <= 0; else @@ -196,6 +204,31 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, end "LEVEL": begin + always @(posedge CLK or RST) begin + + //Main counter + if(KEEP) begin + end + else if(UP) + count <= count + 1'd1; + else + count <= count - 1'd1; + + //Wrapping + if(count == 0 && !UP) + count <= COUNT_TO; + if(count == 14'h3fff && UP) + count <= COUNT_TO; + + //Resets + if(RST) begin + if(RESET_VALUE == "ZERO") + count <= 0; + else + count <= COUNT_TO; + end + + end end default: begin @@ -288,7 +321,7 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; //Resets - if(RST) begin + if(!RST) begin if(RESET_VALUE == "ZERO") count <= 0; else @@ -306,6 +339,31 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, end "LEVEL": begin + always @(posedge CLK or RST) begin + + //Main counter + if(KEEP) begin + end + else if(UP) + count <= count + 1'd1; + else + count <= count - 1'd1; + + //Wrapping + if(count == 0 && !UP) + count <= COUNT_TO; + if(count == 8'hff && UP) + count <= COUNT_TO; + + //Resets + if(RST) begin + if(RESET_VALUE == "ZERO") + count <= 0; + else + count <= COUNT_TO; + end + + end end default: begin @@ -381,6 +439,14 @@ module GP_COUNT8( end "LEVEL": begin + always @(posedge CLK or RST) begin + count <= count - 1'd1; + if(count == 0) + count <= COUNT_TO; + + if(RST) + count <= 0; + end end default: begin |