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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-28 23:16:43 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-28 23:16:43 -0700 |
| commit | 75f0030458a6c5e37238e2437ea469ba9dfd389b (patch) | |
| tree | eebd7258a2720fffb038516ee8754e1550c0eb09 /techlibs/greenpak4 | |
| parent | ea9cc0309245c8d1af5d34b836238f197d34e332 (diff) | |
| download | yosys-75f0030458a6c5e37238e2437ea469ba9dfd389b.tar.gz yosys-75f0030458a6c5e37238e2437ea469ba9dfd389b.tar.bz2 yosys-75f0030458a6c5e37238e2437ea469ba9dfd389b.zip | |
Added keep constraint to GP_SYSRESET cell
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index e22bb80cd..3acea01d2 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -105,6 +105,8 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); endmodule +//keep constraint needed to prevent optimization since we have no outputs +(* keep *) module GP_SYSRESET(input RST); parameter RESET_MODE = "RISING"; |