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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-28 22:49:46 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-28 22:49:46 -0700 |
| commit | ea9cc0309245c8d1af5d34b836238f197d34e332 (patch) | |
| tree | 9a7de10e1b5337bbbbb87bfdc350709952005c11 /techlibs/greenpak4 | |
| parent | 95784437ac237be981d0cf573386ba22f28f9624 (diff) | |
| download | yosys-ea9cc0309245c8d1af5d34b836238f197d34e332.tar.gz yosys-ea9cc0309245c8d1af5d34b836238f197d34e332.tar.bz2 yosys-ea9cc0309245c8d1af5d34b836238f197d34e332.zip | |
Added GP_SYSRESET block
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 6b5100f75..e22bb80cd 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -104,3 +104,10 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); //more complex hard IP blocks are not supported for simulation yet endmodule + +module GP_SYSRESET(input RST); + parameter RESET_MODE = "RISING"; + + //cannot simulate whole system reset + +endmodule |