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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-02 20:27:41 -0700 |
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| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-02 20:27:41 -0700 |
| commit | 79460208c928e62c608d71c0d6d484293835e8dc (patch) | |
| tree | cdf0b578057b2e13c894af92f255b2478b0faf3a /techlibs/greenpak4/cells_sim.v | |
| parent | 12000b90de0bade5fca641c49f3375316220ed39 (diff) | |
| download | yosys-79460208c928e62c608d71c0d6d484293835e8dc.tar.gz yosys-79460208c928e62c608d71c0d6d484293835e8dc.tar.bz2 yosys-79460208c928e62c608d71c0d6d484293835e8dc.zip | |
Added GP_ABUF cell
Diffstat (limited to 'techlibs/greenpak4/cells_sim.v')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index b7dbe81a2..04bce8771 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -13,6 +13,12 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT); assign OUT = INIT[{IN3, IN2, IN1, IN0}]; endmodule +module GP_ABUF(input wire IN, output wire OUT); + + assign OUT = IN; + +endmodule + module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT); parameter BANDWIDTH = "HIGH"; |