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| author | Clifford Wolf <clifford@clifford.at> | 2016-05-02 09:49:07 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-05-02 09:49:07 +0200 |
| commit | 12000b90de0bade5fca641c49f3375316220ed39 (patch) | |
| tree | 0de9d81356e771a246d86da68f625c461942f246 /techlibs/greenpak4/cells_sim.v | |
| parent | 06d35ea9425dbfeff8bcd0d842a31d22843b937b (diff) | |
| parent | 3a85e40f42f4fa52934562135571cfcba35af80e (diff) | |
| download | yosys-12000b90de0bade5fca641c49f3375316220ed39.tar.gz yosys-12000b90de0bade5fca641c49f3375316220ed39.tar.bz2 yosys-12000b90de0bade5fca641c49f3375316220ed39.zip | |
Merge pull request #154 from azonenberg/master
Add GP_PGA cell
Diffstat (limited to 'techlibs/greenpak4/cells_sim.v')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 1152ffe63..b7dbe81a2 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -153,6 +153,17 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT); endmodule +module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT); + + parameter GAIN = 1; + parameter INPUT_MODE = "SINGLE"; + + initial VOUT = 0; + + //cannot simulate mixed signal IP + +endmodule + module GP_POR(output reg RST_DONE); parameter POR_TIME = 500; |