Merge branch 'master' into xaig

2 files changed, 7 insertions, 7 deletions

diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v
index 25e789e4a..e15de6423 100644
--- a/techlibs/gowin/arith_map.v
+++ b/techlibs/gowin/arith_map.v
@@ -25,24 +25,24 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
    parameter A_WIDTH = 1;
    parameter B_WIDTH = 1;
    parameter Y_WIDTH = 1;
-   
+
    input [A_WIDTH-1:0] A;
    input [B_WIDTH-1:0] B;
    output [Y_WIDTH-1:0] X, Y;
-   
+
    input 		CI, BI;
    output [Y_WIDTH-1:0] CO;
-   
+
    wire 		_TECHMAP_FAIL_ = Y_WIDTH <= 2;
-   
+
    wire [Y_WIDTH-1:0] 	A_buf, B_buf;
    \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
    \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-   
+
    wire [Y_WIDTH-1:0] 	AA = A_buf;
    wire [Y_WIDTH-1:0] 	BB = BI ? ~B_buf : B_buf;
    wire [Y_WIDTH-1:0] 	C = {CO, CI};
-   
+
    genvar 		i;
    generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
       ALU #(.ALU_MODE(32'b0))
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 96128a680..9a3fcdbb6 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -111,7 +111,7 @@ struct SynthGowinPass : public ScriptPass
 			if (args[argidx] == "-noflatten") {
 				flatten = false;
 				continue;
-			}			
+			}
 			break;
 		}
 		extra_args(args, argidx, design);