synth_gatemate: Revise block RAM read modes and initialization

* enable mixed read-width / write-width ports in SDP mode
* fix NO_CHANGE and WRITE_THROUGH behavior during read access
* remove redundant zero-initialization
* set A/B_WE bit during map (gatemate_bramopt pass could be removed later)
* differentiate "upper" and "lower" initialization for cascade mode

3 files changed, 230 insertions, 71 deletions

diff --git a/techlibs/gatemate/brams_init_40.vh b/techlibs/gatemate/brams_init_40.vh
index ccf14bca8..649342560 100644
--- a/techlibs/gatemate/brams_init_40.vh
+++ b/techlibs/gatemate/brams_init_40.vh
@@ -1,3 +1,4 @@
+`ifdef INIT_LOWER
 .INIT_00(permute_init(INIT[  0*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
 .INIT_01(permute_init(INIT[  1*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
 .INIT_02(permute_init(INIT[  2*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
@@ -126,3 +127,134 @@
 .INIT_7D(permute_init(INIT[125*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
 .INIT_7E(permute_init(INIT[126*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
 .INIT_7F(permute_init(INIT[127*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+`endif
+`ifdef INIT_UPPER
+.INIT_00(permute_init(INIT[128*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_01(permute_init(INIT[129*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_02(permute_init(INIT[130*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_03(permute_init(INIT[131*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_04(permute_init(INIT[132*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_05(permute_init(INIT[133*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_06(permute_init(INIT[134*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_07(permute_init(INIT[135*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_08(permute_init(INIT[136*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_09(permute_init(INIT[137*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_0A(permute_init(INIT[138*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_0B(permute_init(INIT[139*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_0C(permute_init(INIT[140*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_0D(permute_init(INIT[141*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_0E(permute_init(INIT[142*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_0F(permute_init(INIT[143*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_10(permute_init(INIT[144*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_11(permute_init(INIT[145*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_12(permute_init(INIT[146*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_13(permute_init(INIT[147*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_14(permute_init(INIT[148*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_15(permute_init(INIT[149*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_16(permute_init(INIT[150*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_17(permute_init(INIT[151*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_18(permute_init(INIT[152*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_19(permute_init(INIT[153*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_1A(permute_init(INIT[154*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_1B(permute_init(INIT[155*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_1C(permute_init(INIT[156*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_1D(permute_init(INIT[157*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_1E(permute_init(INIT[158*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_1F(permute_init(INIT[159*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_20(permute_init(INIT[160*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_21(permute_init(INIT[161*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_22(permute_init(INIT[162*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_23(permute_init(INIT[163*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_24(permute_init(INIT[164*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_25(permute_init(INIT[165*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_26(permute_init(INIT[166*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_27(permute_init(INIT[167*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_28(permute_init(INIT[168*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_29(permute_init(INIT[169*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_2A(permute_init(INIT[170*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_2B(permute_init(INIT[171*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_2C(permute_init(INIT[172*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_2D(permute_init(INIT[173*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_2E(permute_init(INIT[174*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_2F(permute_init(INIT[175*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_30(permute_init(INIT[176*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_31(permute_init(INIT[177*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_32(permute_init(INIT[178*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_33(permute_init(INIT[179*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_34(permute_init(INIT[180*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_35(permute_init(INIT[181*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_36(permute_init(INIT[182*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_37(permute_init(INIT[183*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_38(permute_init(INIT[184*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_39(permute_init(INIT[185*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_3A(permute_init(INIT[186*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_3B(permute_init(INIT[187*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_3C(permute_init(INIT[188*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_3D(permute_init(INIT[189*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_3E(permute_init(INIT[190*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_3F(permute_init(INIT[191*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_40(permute_init(INIT[192*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_41(permute_init(INIT[193*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_42(permute_init(INIT[194*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_43(permute_init(INIT[195*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_44(permute_init(INIT[196*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_45(permute_init(INIT[197*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_46(permute_init(INIT[198*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_47(permute_init(INIT[199*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_48(permute_init(INIT[200*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_49(permute_init(INIT[201*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_4A(permute_init(INIT[202*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_4B(permute_init(INIT[203*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_4C(permute_init(INIT[204*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_4D(permute_init(INIT[205*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_4E(permute_init(INIT[206*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_4F(permute_init(INIT[207*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_50(permute_init(INIT[208*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_51(permute_init(INIT[209*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_52(permute_init(INIT[210*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_53(permute_init(INIT[211*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_54(permute_init(INIT[212*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_55(permute_init(INIT[213*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_56(permute_init(INIT[214*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_57(permute_init(INIT[215*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_58(permute_init(INIT[216*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_59(permute_init(INIT[217*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_5A(permute_init(INIT[218*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_5B(permute_init(INIT[219*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_5C(permute_init(INIT[220*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_5D(permute_init(INIT[221*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_5E(permute_init(INIT[222*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_5F(permute_init(INIT[223*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_60(permute_init(INIT[224*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_61(permute_init(INIT[225*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_62(permute_init(INIT[226*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_63(permute_init(INIT[227*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_64(permute_init(INIT[228*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_65(permute_init(INIT[229*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_66(permute_init(INIT[230*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_67(permute_init(INIT[231*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_68(permute_init(INIT[232*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_69(permute_init(INIT[233*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_6A(permute_init(INIT[234*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_6B(permute_init(INIT[235*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_6C(permute_init(INIT[236*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_6D(permute_init(INIT[237*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_6E(permute_init(INIT[238*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_6F(permute_init(INIT[239*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_70(permute_init(INIT[240*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_71(permute_init(INIT[241*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_72(permute_init(INIT[242*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_73(permute_init(INIT[243*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_74(permute_init(INIT[244*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_75(permute_init(INIT[245*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_76(permute_init(INIT[246*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_77(permute_init(INIT[247*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_78(permute_init(INIT[248*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_79(permute_init(INIT[249*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_7A(permute_init(INIT[250*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_7B(permute_init(INIT[251*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_7C(permute_init(INIT[252*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_7D(permute_init(INIT[253*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_7E(permute_init(INIT[254*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+.INIT_7F(permute_init(INIT[255*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),
+`endif
diff --git a/techlibs/gatemate/brams_map.v b/techlibs/gatemate/brams_map.v
index eaaf146ac..b7f0ff73e 100644
--- a/techlibs/gatemate/brams_map.v
+++ b/techlibs/gatemate/brams_map.v
@@ -58,12 +58,7 @@ module \$__CC_BRAM_20K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 		begin

 			if (CFG_DBITS <= 2) begin

 				for (i = 0; i < 64; i = i + 1) begin

-					if (^chunk[i * 4 +: 4] === 1'bx) begin

-						permute_init[i * 5 +: 5] = 5'b0;

-					end

-					else begin

-						permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};

-					end

+					permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};

 				end

 			end else begin

 				permute_init = chunk;

@@ -92,7 +87,7 @@ module \$__CC_BRAM_20K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 		.B_CLK(CLK3),

 		.A_EN(1'b1),

 		.B_EN(B1EN),

-		.A_WE(1'b1),

+		.A_WE(|A1EN),

 		.B_WE(1'b0),

 		.A_ADDR(ADDRA),

 		.B_ADDR(ADDRB),

@@ -146,12 +141,7 @@ module \$__CC_BRAM_40K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 		begin

 			if (CFG_DBITS <= 2) begin

 				for (i = 0; i < 64; i = i + 1) begin

-					if (^chunk[i * 4 +: 4] === 1'bx) begin

-						permute_init[i * 5 +: 5] = 5'b0;

-					end

-					else begin

-						permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};

-					end

+					permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};

 				end

 			end else begin

 				permute_init = chunk;

@@ -160,7 +150,9 @@ module \$__CC_BRAM_40K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 	endfunction

 

 	CC_BRAM_40K #(

+		`define INIT_LOWER

 		`include "brams_init_40.vh"

+		`undef INIT_LOWER

 		.LOC("UNPLACED"),

 		.CAS("NONE"),

 		.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),

@@ -181,9 +173,9 @@ module \$__CC_BRAM_40K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 		.B_ECC_2B_ERR(B_ECC_2B_ERR),

 		.A_CLK(CLK2),

 		.B_CLK(CLK3),

-		.A_EN(1'b1),

+		.A_EN(|A1EN),

 		.B_EN(B1EN),

-		.A_WE(1'b1),

+		.A_WE(|A1EN),

 		.B_WE(1'b0),

 		.A_ADDR(ADDRA),

 		.B_ADDR(ADDRB),

@@ -234,12 +226,7 @@ module \$__CC_BRAM_20K_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 		begin

 			if (CFG_DBITS <= 2) begin

 				for (i = 0; i < 64; i = i + 1) begin

-					if (^chunk[i * 4 +: 4] === 1'bx) begin

-						permute_init[i * 5 +: 5] = 5'b0;

-					end

-					else begin

-						permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};

-					end

+					permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};

 				end

 			end else begin

 				permute_init = chunk;

@@ -294,7 +281,7 @@ module \$__CC_BRAM_20K_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 			.B_CLK(CLK3),

 			.A_EN(1'b1),

 			.B_EN(B1EN),

-			.A_WE(1'b1),

+			.A_WE(|A1EN),

 			.B_WE(1'b0),

 			.A_ADDR(ADDRA),

 			.B_ADDR(ADDRB),

@@ -346,7 +333,7 @@ module \$__CC_BRAM_40K_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 		begin

 			if (CFG_DBITS <= 2) begin

 				for (i = 0; i < 64; i = i + 1) begin

-					permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]} & 5'b11111;

+					permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};

 				end

 			end else begin

 				permute_init = chunk;

@@ -384,7 +371,9 @@ module \$__CC_BRAM_40K_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 		end

 

 		CC_BRAM_40K #(

+			`define INIT_LOWER

 			`include "brams_init_40.vh"

+			`undef INIT_LOWER

 			.LOC("UNPLACED"),

 			.CAS("NONE"),

 			.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),

@@ -407,7 +396,7 @@ module \$__CC_BRAM_40K_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 			.B_CLK(CLK3),

 			.A_EN(1'b1),

 			.B_EN(B1EN),

-			.A_WE(1'b1),

+			.A_WE(|A1EN),

 			.B_WE(1'b0),

 			.A_ADDR(ADDRA),

 			.B_ADDR(ADDRB),

@@ -461,14 +450,16 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 		integer i;

 		begin

 			for (i = 0; i < 64; i = i + 1) begin

-				permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]} & 5'b11111;

+				permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};

 			end

 		end

 	endfunction

 

 	generate

 		CC_BRAM_40K #(

-			`include "brams_init_40.vh"

+			`define INIT_UPPER

+			`include "brams_init_40.vh" // INIT_80 .. INIT_FF

+			`undef INIT_UPPER

 			.LOC("UNPLACED"),

 			.CAS("UPPER"),

 			.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),

@@ -493,7 +484,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 			.B_CLK(CLK3),

 			.A_EN(1'b1),

 			.B_EN(B1EN),

-			.A_WE(1'b1),

+			.A_WE(|A1EN),

 			.B_WE(1'b0),

 			.A_ADDR(A1ADDR),

 			.B_ADDR(B1ADDR),

@@ -504,7 +495,9 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 		);

 

 		CC_BRAM_40K #(

-			`include "brams_init_40.vh"

+			`define INIT_LOWER

+			`include "brams_init_40.vh" // INIT_00 .. INIT_7F

+			`undef INIT_LOWER

 			.LOC("UNPLACED"),

 			.CAS("LOWER"),

 			.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),

@@ -525,7 +518,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
 			.B_CLK(CLK3),

 			.A_EN(1'b1),

 			.B_EN(B1EN),

-			.A_WE(1'b1),

+			.A_WE(|A1EN),

 			.B_WE(1'b0),

 			.A_ADDR(A1ADDR),

 			.B_ADDR(B1ADDR),

diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v
index c1cacc6d1..9b62ea6ee 100644
--- a/techlibs/gatemate/cells_sim.v
+++ b/techlibs/gatemate/cells_sim.v
@@ -758,41 +758,41 @@ module CC_BRAM_20K (
 	generate

 		if (RAM_MODE == "SDP") begin

 			// Port A (write)

-			if (WIDTH_MODE_A <= 1) begin

+			if (A_WR_WIDTH <= 1) begin

 				assign addra = A_ADDR[15:7] + (A_ADDR[15:7]/4);

 			end

-			if (WIDTH_MODE_A <= 2) begin

+			else if (A_WR_WIDTH <= 2) begin

 				assign addra = A_ADDR[15:7]*2 + (A_ADDR[15:7]/2);

 			end

-			else if (WIDTH_MODE_A <= 5) begin

+			else if (A_WR_WIDTH <= 5) begin

 				assign addra = A_ADDR[15:7]*5;

 			end

-			else if (WIDTH_MODE_A <= 10) begin

+			else if (A_WR_WIDTH <= 10) begin

 				assign addra = A_ADDR[15:7]*10;

 			end

-			else if (WIDTH_MODE_A <= 20) begin

+			else if (A_WR_WIDTH <= 20) begin

 				assign addra = A_ADDR[15:7]*20;

 			end

-			else if (WIDTH_MODE_A <= 40) begin

+			else if (A_WR_WIDTH <= 40) begin

 				assign addra = A_ADDR[15:7]*40;

 			end

 			// Port B (read)

-			if (WIDTH_MODE_B <= 1) begin

+			if (B_RD_WIDTH <= 1) begin

 				assign addrb = B_ADDR[15:7] + (B_ADDR[15:7]/4);

 			end

-			else if (WIDTH_MODE_B <= 2) begin

+			else if (B_RD_WIDTH <= 2) begin

 				assign addrb = B_ADDR[15:7]*2 + (B_ADDR[15:7]/2);

 			end

-			else if (WIDTH_MODE_B <= 5) begin

+			else if (B_RD_WIDTH <= 5) begin

 				assign addrb = B_ADDR[15:7]*5;

 			end

-			else if (WIDTH_MODE_B <= 10) begin

+			else if (B_RD_WIDTH <= 10) begin

 				assign addrb = B_ADDR[15:7]*10;

 			end

-			else if (WIDTH_MODE_B <= 20) begin

+			else if (B_RD_WIDTH <= 20) begin

 				assign addrb = B_ADDR[15:7]*20;

 			end

-			else if (WIDTH_MODE_B <= 40) begin

+			else if (B_RD_WIDTH <= 40) begin

 				assign addrb = B_ADDR[15:7]*40;

 			end

 		end

@@ -841,7 +841,7 @@ module CC_BRAM_20K (
 			// SDP write port

 			always @(posedge clka)

 			begin

-				for (k=0; k < WIDTH_MODE_A; k=k+1) begin

+				for (k=0; k < A_WR_WIDTH; k=k+1) begin

 					if (k < 20) begin

 						if (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k];

 					end

@@ -853,12 +853,13 @@ module CC_BRAM_20K (
 			// SDP read port

 			always @(posedge clkb)

 			begin

-				for (k=0; k < WIDTH_MODE_B; k=k+1) begin

+				// "NO_CHANGE" only

+				for (k=0; k < B_RD_WIDTH; k=k+1) begin

 					if (k < 20) begin

-						if (enb) A_DO_out[k] <= memory[addrb+k];

+						if (enb && !wea) A_DO_out[k] <= memory[addrb+k];

 					end

 					else begin // use both ports

-						if (enb) B_DO_out[k-20] <= memory[addrb+k];

+						if (enb && !wea) B_DO_out[k-20] <= memory[addrb+k];

 					end

 				end

 			end

@@ -871,10 +872,17 @@ module CC_BRAM_20K (
 					if (ena && wea && A_BM[i]) memory[addra+i] <= A_DI[i];

 

 					if (A_WR_MODE == "NO_CHANGE") begin

-						if (ena) A_DO_out[i] <= memory[addra+i];

+						if (ena && !wea) A_DO_out[i] <= memory[addra+i];

 					end

 					else if (A_WR_MODE == "WRITE_THROUGH") begin

-						if (ena) A_DO_out[i] <= A_DI[i];

+						if (ena) begin

+							if (wea && A_BM[i]) begin

+								A_DO_out[i] <= A_DI[i];

+							end

+							else begin

+								A_DO_out[i] <= memory[addra+i];

+							end

+						end

 					end

 				end

 			end

@@ -885,10 +893,17 @@ module CC_BRAM_20K (
 					if (enb && web && B_BM[i]) memory[addrb+i] <= B_DI[i];

 

 					if (B_WR_MODE == "NO_CHANGE") begin

-						if (enb) B_DO_out[i] <= memory[addrb+i];

+						if (enb && !web) B_DO_out[i] <= memory[addrb+i];

 					end

 					else if (B_WR_MODE == "WRITE_THROUGH") begin

-						if (enb) B_DO_out[i] <= B_DI[i];

+						if (enb) begin

+							if (web && B_BM[i]) begin

+								B_DO_out[i] <= B_DI[i];

+							end

+							else begin

+								B_DO_out[i] <= memory[addrb+i];

+							end

+						end

 					end

 				end

 			end

@@ -1152,6 +1167,10 @@ module CC_BRAM_40K (
 			$display("ERROR: Illegal %s Port B width configuration %d.", RAM_MODE, WIDTH_MODE_B);

 			$finish();

 		end

+		if (CAS != "NONE") begin

+			$display("WARNING: Cascade simulation model not yet supported.");

+			$finish();

+		end

 		if ((CAS != "NONE") && ((WIDTH_MODE_A > 1) || (WIDTH_MODE_B > 1))) begin

 			$display("ERROR: Cascade feature only supported in 1 bit data width mode.");

 			$finish();

@@ -1308,47 +1327,47 @@ module CC_BRAM_40K (
 	generate

 		if (RAM_MODE == "SDP") begin

 			// Port A (write)

-			if (WIDTH_MODE_A <= 1) begin

+			if (A_WR_WIDTH <= 1) begin

 				assign addra = A_ADDR[15:7] + (A_ADDR[15:7]/4);

 			end

-			if (WIDTH_MODE_A <= 2) begin

+			else if (A_WR_WIDTH <= 2) begin

 				assign addra = A_ADDR[15:7]*2 + (A_ADDR[15:7]/2);

 			end

-			else if (WIDTH_MODE_A <= 5) begin

+			else if (A_WR_WIDTH <= 5) begin

 				assign addra = A_ADDR[15:7]*5;

 			end

-			else if (WIDTH_MODE_A <= 10) begin

+			else if (A_WR_WIDTH <= 10) begin

 				assign addra = A_ADDR[15:7]*10;

 			end

-			else if (WIDTH_MODE_A <= 20) begin

+			else if (A_WR_WIDTH <= 20) begin

 				assign addra = A_ADDR[15:7]*20;

 			end

-			else if (WIDTH_MODE_A <= 40) begin

+			else if (A_WR_WIDTH <= 40) begin

 				assign addra = A_ADDR[15:7]*40;

 			end

-			else if (WIDTH_MODE_A <= 80) begin

+			else if (A_WR_WIDTH <= 80) begin

 				assign addra = A_ADDR[15:7]*80;

 			end

 			// Port B (read)

-			if (WIDTH_MODE_B <= 1) begin

+			if (B_RD_WIDTH <= 1) begin

 				assign addrb = B_ADDR[15:7] + (B_ADDR[15:7]/4);

 			end

-			else if (WIDTH_MODE_B <= 2) begin

+			else if (B_RD_WIDTH <= 2) begin

 				assign addrb = B_ADDR[15:7]*2 + (B_ADDR[15:7]/2);

 			end

-			else if (WIDTH_MODE_B <= 5) begin

+			else if (B_RD_WIDTH <= 5) begin

 				assign addrb = B_ADDR[15:7]*5;

 			end

-			else if (WIDTH_MODE_B <= 10) begin

+			else if (B_RD_WIDTH <= 10) begin

 				assign addrb = B_ADDR[15:7]*10;

 			end

-			else if (WIDTH_MODE_B <= 20) begin

+			else if (B_RD_WIDTH <= 20) begin

 				assign addrb = B_ADDR[15:7]*20;

 			end

-			else if (WIDTH_MODE_B <= 40) begin

+			else if (B_RD_WIDTH <= 40) begin

 				assign addrb = B_ADDR[15:7]*40;

 			end

-			else if (WIDTH_MODE_B <= 80) begin

+			else if (B_RD_WIDTH <= 80) begin

 				assign addrb = B_ADDR[15:7]*80;

 			end

 		end

@@ -1403,7 +1422,7 @@ module CC_BRAM_40K (
 			// SDP write port

 			always @(posedge clka)

 			begin

-				for (k=0; k < WIDTH_MODE_A; k=k+1) begin

+				for (k=0; k < A_WR_WIDTH; k=k+1) begin

 					if (k < 40) begin

 						if (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k];

 					end

@@ -1415,12 +1434,13 @@ module CC_BRAM_40K (
 			// SDP read port

 			always @(posedge clkb)

 			begin

-				for (k=0; k < WIDTH_MODE_B; k=k+1) begin

+				// "NO_CHANGE" only

+				for (k=0; k < B_RD_WIDTH; k=k+1) begin

 					if (k < 40) begin

-						if (enb) A_DO_out[k] <= memory[addrb+k];

+						if (enb && !wea) A_DO_out[k] <= memory[addrb+k];

 					end

 					else begin // use both ports

-						if (enb) B_DO_out[k-40] <= memory[addrb+k];

+						if (enb && !wea) B_DO_out[k-40] <= memory[addrb+k];

 					end

 				end

 			end

@@ -1433,10 +1453,17 @@ module CC_BRAM_40K (
 					if (ena && wea && A_BM[i]) memory[addra+i] <= A_DI[i];

 

 					if (A_WR_MODE == "NO_CHANGE") begin

-						if (ena) A_DO_out[i] <= memory[addra+i];

+						if (ena && !wea) A_DO_out[i] <= memory[addra+i];

 					end

 					else if (A_WR_MODE == "WRITE_THROUGH") begin

-						if (ena) A_DO_out[i] <= A_DI[i];

+						if (ena) begin

+							if (wea && A_BM[i]) begin

+								A_DO_out[i] <= A_DI[i];

+							end

+							else begin

+								A_DO_out[i] <= memory[addra+i];

+							end

+						end

 					end

 				end

 			end

@@ -1447,10 +1474,17 @@ module CC_BRAM_40K (
 					if (enb && web && B_BM[i]) memory[addrb+i] <= B_DI[i];

 

 					if (B_WR_MODE == "NO_CHANGE") begin

-						if (enb) B_DO_out[i] <= memory[addrb+i];

+						if (enb && !web) B_DO_out[i] <= memory[addrb+i];

 					end

 					else if (B_WR_MODE == "WRITE_THROUGH") begin

-						if (enb) B_DO_out[i] <= B_DI[i];

+						if (enb) begin

+							if (web && B_BM[i]) begin

+								B_DO_out[i] <= B_DI[i];

+							end

+							else begin

+								B_DO_out[i] <= memory[addrb+i];

+							end

+						end

 					end

 				end

 			end