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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-04 11:44:00 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-04 11:44:00 -0700 |
| commit | e6b55e8b38d98e28ee53f7b470cef1bcc3b399f3 (patch) | |
| tree | e0a5854f4af16f8fa091c7f0fcd7695756fdea61 /techlibs/ecp5/synth_ecp5.cc | |
| parent | 584780d776c92bc91731dbc2710dd8d9a624dc70 (diff) | |
| download | yosys-e6b55e8b38d98e28ee53f7b470cef1bcc3b399f3.tar.gz yosys-e6b55e8b38d98e28ee53f7b470cef1bcc3b399f3.tar.bz2 yosys-e6b55e8b38d98e28ee53f7b470cef1bcc3b399f3.zip | |
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
Diffstat (limited to 'techlibs/ecp5/synth_ecp5.cc')
| -rw-r--r-- | techlibs/ecp5/synth_ecp5.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index ab740ea0d..b9b236a0c 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -30,6 +30,11 @@ struct SynthEcp5Pass : public ScriptPass { SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { } + void on_register() YS_OVERRIDE + { + RTLIL::constpad["synth_ecp5.abc9.W"] = "300"; + } + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -324,6 +329,14 @@ struct SynthEcp5Pass : public ScriptPass if (abc9) { run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v"); + std::string abc9_opts; + if (nowidelut) + abc9_opts += " -maxlut 4"; + std::string k = "synth_ecp5.abc9.W"; + if (active_design && active_design->scratchpad.count(k)) + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + else + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); if (nowidelut) run("abc9 -maxlut 4 -W 200"); else |