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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-08 10:43:38 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-08 10:43:38 +0100 |
| commit | fad9cec47b3aa9fc3d413abee92cc8380d0c0dc4 (patch) | |
| tree | 95a4380aa94a740d13a291fb6d11437ac1081c38 /techlibs/common | |
| parent | 2903143ae50301dca08d1ab671a046184e8d7c46 (diff) | |
| download | yosys-fad9cec47b3aa9fc3d413abee92cc8380d0c0dc4.tar.gz yosys-fad9cec47b3aa9fc3d413abee92cc8380d0c0dc4.tar.bz2 yosys-fad9cec47b3aa9fc3d413abee92cc8380d0c0dc4.zip | |
Added $_DFFE_??_ cell types
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/simcells.v | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 88566411a..eb62d7830 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -163,6 +163,38 @@ always @(posedge C) begin end endmodule +module \$_DFFE_NN_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(negedge C) begin + if (!E) Q <= D; +end +endmodule + +module \$_DFFE_NP_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(negedge C) begin + if (E) Q <= D; +end +endmodule + +module \$_DFFE_PN_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(posedge C) begin + if (!E) Q <= D; +end +endmodule + +module \$_DFFE_PP_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(posedge C) begin + if (E) Q <= D; +end +endmodule + module \$_DFF_NN0_ (D, Q, C, R); input D, C, R; output reg Q; |