From fad9cec47b3aa9fc3d413abee92cc8380d0c0dc4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 8 Dec 2014 10:43:38 +0100 Subject: Added $_DFFE_??_ cell types --- techlibs/common/simcells.v | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'techlibs/common') diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 88566411a..eb62d7830 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -163,6 +163,38 @@ always @(posedge C) begin end endmodule +module \$_DFFE_NN_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(negedge C) begin + if (!E) Q <= D; +end +endmodule + +module \$_DFFE_NP_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(negedge C) begin + if (E) Q <= D; +end +endmodule + +module \$_DFFE_PN_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(posedge C) begin + if (!E) Q <= D; +end +endmodule + +module \$_DFFE_PP_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(posedge C) begin + if (E) Q <= D; +end +endmodule + module \$_DFF_NN0_ (D, Q, C, R); input D, C, R; output reg Q; -- cgit v1.2.3