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| author | clairexen <claire@symbioticeda.com> | 2020-07-16 18:28:24 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-16 18:28:24 +0200 |
| commit | c49344b262b455bf03239a5bc7453f0706cc45d8 (patch) | |
| tree | c628628470ee3862d4a12833de6f6c9a7e11d765 /techlibs/anlogic | |
| parent | 910f4213247a69e1214aac70a552eec0a21d4275 (diff) | |
| parent | d9f680b2363aded426465fd189910e0072228fee (diff) | |
| download | yosys-c49344b262b455bf03239a5bc7453f0706cc45d8.tar.gz yosys-c49344b262b455bf03239a5bc7453f0706cc45d8.tar.bz2 yosys-c49344b262b455bf03239a5bc7453f0706cc45d8.zip | |
Merge pull request #2272 from whitequark/write-verilog-sv
verilog_backend: add `-sv` option, make `-o <filename>.sv` work
Diffstat (limited to 'techlibs/anlogic')
0 files changed, 0 insertions, 0 deletions