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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-11 22:10:17 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-11 22:10:17 -0700 |
| commit | ba1a428f550d2bac91a442ccd04cb9e70833d093 (patch) | |
| tree | 106f178d42a54403218f93cae2807d6e67981599 /techlibs/anlogic | |
| parent | c851dc13108021834533094a8a3236da6d9e0161 (diff) | |
| parent | 88d5185596a0cc8319658463a31b20644d90dd6b (diff) | |
| download | yosys-ba1a428f550d2bac91a442ccd04cb9e70833d093.tar.gz yosys-ba1a428f550d2bac91a442ccd04cb9e70833d093.tar.bz2 yosys-ba1a428f550d2bac91a442ccd04cb9e70833d093.zip | |
Merge pull request #1277 from YosysHQ/eddie/fix_1262
opt_expr -fine to now trim LSBs of $alu cells too
Diffstat (limited to 'techlibs/anlogic')
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