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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-08 03:52:16 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-18 17:32:56 +0200 |
| commit | a04b025abff798f37d580a7d30084497d61d0fe0 (patch) | |
| tree | 9b9d78548059437381e384c611fa5397d46fb76d /techlibs/anlogic/synth_anlogic.cc | |
| parent | 7c5dba8b77571aa6a2c0c38eeed7963b401d1cbd (diff) | |
| download | yosys-a04b025abff798f37d580a7d30084497d61d0fe0.tar.gz yosys-a04b025abff798f37d580a7d30084497d61d0fe0.tar.bz2 yosys-a04b025abff798f37d580a7d30084497d61d0fe0.zip | |
ecp5: Use `memory_libmap` pass.
Diffstat (limited to 'techlibs/anlogic/synth_anlogic.cc')
0 files changed, 0 insertions, 0 deletions