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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-06 10:10:21 +0100 |
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| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-18 17:32:56 +0200 |
| commit | 7c5dba8b77571aa6a2c0c38eeed7963b401d1cbd (patch) | |
| tree | f860b6ac949f2386bfb4856bb7e347692f9399ff /techlibs/anlogic/synth_anlogic.cc | |
| parent | 9450f308f07ea61a072da4377770ed36b0ce9a45 (diff) | |
| download | yosys-7c5dba8b77571aa6a2c0c38eeed7963b401d1cbd.tar.gz yosys-7c5dba8b77571aa6a2c0c38eeed7963b401d1cbd.tar.bz2 yosys-7c5dba8b77571aa6a2c0c38eeed7963b401d1cbd.zip | |
Add memory_libmap pass.
Diffstat (limited to 'techlibs/anlogic/synth_anlogic.cc')
0 files changed, 0 insertions, 0 deletions