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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-17 17:16:10 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-17 17:16:10 +0100 |
| commit | 847fd360773d72933f1c728dba0755e0033350a6 (patch) | |
| tree | 0366fa1ca596e67aa583b540eb3b2e910bcc4c04 /techlibs/anlogic/synth_anlogic.cc | |
| parent | 3b4290a1b822aca42ceab4a89043329cb060325d (diff) | |
| parent | d53a2bd1d3ae3cfbc9ead0fc12999fe269628179 (diff) | |
| download | yosys-847fd360773d72933f1c728dba0755e0033350a6.tar.gz yosys-847fd360773d72933f1c728dba0755e0033350a6.tar.bz2 yosys-847fd360773d72933f1c728dba0755e0033350a6.zip | |
Merge pull request #746 from Icenowy/anlogic-dram
Support for DRAM inferring on Anlogic FPGAs
Diffstat (limited to 'techlibs/anlogic/synth_anlogic.cc')
| -rw-r--r-- | techlibs/anlogic/synth_anlogic.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index f4ef88770..a4eafeddf 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -150,6 +150,12 @@ struct SynthAnlogicPass : public ScriptPass run("synth -run coarse"); } + if (check_label("dram")) + { + run("memory_bram -rules +/anlogic/drams.txt"); + run("techmap -map +/anlogic/drams_map.v"); + } + if (check_label("fine")) { run("opt -fast -mux_undef -undriven -fine"); |