From d53a2bd1d3ae3cfbc9ead0fc12999fe269628179 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 14 Dec 2018 16:50:37 +0800 Subject: anlogic: add support for Eagle Distributed RAM The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng --- techlibs/anlogic/synth_anlogic.cc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'techlibs/anlogic/synth_anlogic.cc') diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index f4ef88770..a4eafeddf 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -150,6 +150,12 @@ struct SynthAnlogicPass : public ScriptPass run("synth -run coarse"); } + if (check_label("dram")) + { + run("memory_bram -rules +/anlogic/drams.txt"); + run("techmap -map +/anlogic/drams_map.v"); + } + if (check_label("fine")) { run("opt -fast -mux_undef -undriven -fine"); -- cgit v1.2.3