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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-04-08 20:54:31 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-04-12 15:11:09 +0200 |
| commit | 2021ddecb39d3848e180cd7e078facf82132440f (patch) | |
| tree | a768dd33906dae73482f79cd78c8bce8ddd56f0d /techlibs/altera_intel/synth_intel.cc | |
| parent | 41d4e91f388f41c97f71567cd5a0f5652a5968fd (diff) | |
| download | yosys-2021ddecb39d3848e180cd7e078facf82132440f.tar.gz yosys-2021ddecb39d3848e180cd7e078facf82132440f.tar.bz2 yosys-2021ddecb39d3848e180cd7e078facf82132440f.zip | |
Squelch trailing whitespace
Diffstat (limited to 'techlibs/altera_intel/synth_intel.cc')
| -rw-r--r-- | techlibs/altera_intel/synth_intel.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/altera_intel/synth_intel.cc b/techlibs/altera_intel/synth_intel.cc index 9710f7a85..003059458 100644 --- a/techlibs/altera_intel/synth_intel.cc +++ b/techlibs/altera_intel/synth_intel.cc @@ -110,7 +110,7 @@ struct SynthIntelPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This comannd only operates on fully selected designs!\n"); - + if (family_opt != "max10" && family_opt !="cycloneiv" ) log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str()); |