Merge pull request #453 from dh73/master

Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells

5 files changed, 4 insertions, 4 deletions

diff --git a/techlibs/achronix/Makefile.inc b/techlibs/achronix/Makefile.inc
index 4dfa59856..affe0334a 100755
--- a/techlibs/achronix/Makefile.inc
+++ b/techlibs/achronix/Makefile.inc
@@ -1,6 +1,6 @@
 
 OBJS += techlibs/achronix/synth_speedster.o
 
-$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_comb_speedster.v))
-$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map_speedster.v))
+$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v))
+$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v))
 
diff --git a/techlibs/achronix/speedster22i/cells_arith_speedster.v b/techlibs/achronix/speedster22i/cells_arith.v
index 9ef073f7c..9ef073f7c 100755
--- a/techlibs/achronix/speedster22i/cells_arith_speedster.v
+++ b/techlibs/achronix/speedster22i/cells_arith.v
diff --git a/techlibs/achronix/speedster22i/cells_map_speedster.v b/techlibs/achronix/speedster22i/cells_map.v
index fb26eabf0..fb26eabf0 100755
--- a/techlibs/achronix/speedster22i/cells_map_speedster.v
+++ b/techlibs/achronix/speedster22i/cells_map.v
diff --git a/techlibs/achronix/speedster22i/cells_comb_speedster.v b/techlibs/achronix/speedster22i/cells_sim.v
index 24c57c41a..24c57c41a 100755
--- a/techlibs/achronix/speedster22i/cells_comb_speedster.v
+++ b/techlibs/achronix/speedster22i/cells_sim.v
diff --git a/techlibs/achronix/synth_speedster.cc b/techlibs/achronix/synth_speedster.cc
index 8158c56fd..3808af6f1 100755
--- a/techlibs/achronix/synth_speedster.cc
+++ b/techlibs/achronix/synth_speedster.cc
@@ -122,7 +122,7 @@ struct SynthIntelPass : public ScriptPass {
   {
     if (check_label("begin"))
       {
-        run("read_verilog -sv -lib +/achronix/speedster22i/cells_comb_speedster.v");
+        run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
       }
 
@@ -164,7 +164,7 @@ struct SynthIntelPass : public ScriptPass {
     if (check_label("map_cells"))
       {
         run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
-        run("techmap -map +/achronix/speedster22i/cells_map_speedster.v");
+        run("techmap -map +/achronix/speedster22i/cells_map.v");
         run("dffinit -ff dffeas Q INIT");
         run("clean -purge");
       }