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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-21 12:32:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | e2044fd9c7de4534428ee4f3e8cf1448c493a7fc (patch) | |
| tree | 5a9bcb8538bb8cf79e0254c31a2ac1794e6b2bf9 /passes | |
| parent | 8b5fb99245969f62068e3b0b118d7b553ee628e8 (diff) | |
| download | yosys-e2044fd9c7de4534428ee4f3e8cf1448c493a7fc.tar.gz yosys-e2044fd9c7de4534428ee4f3e8cf1448c493a7fc.tar.bz2 yosys-e2044fd9c7de4534428ee4f3e8cf1448c493a7fc.zip | |
abc9_ops: -prep_delays to not insert delay box if input connection is const
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index bc20d4731..d7280e3fd 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -804,6 +804,8 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) log_id(conn.first), log_id(cell->name), log_id(cell->type), log_id(module->name)); if (!port_wire->port_input) continue; + if (conn.second.is_fully_const()) + continue; SigSpec O = module->addWire(NEW_ID, GetSize(conn.second)); for (int i = 0; i < GetSize(conn.second); i++) { |