From e2044fd9c7de4534428ee4f3e8cf1448c493a7fc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 21 Apr 2020 12:32:30 -0700 Subject: abc9_ops: -prep_delays to not insert delay box if input connection is const --- passes/techmap/abc9_ops.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'passes') diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index bc20d4731..d7280e3fd 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -804,6 +804,8 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) log_id(conn.first), log_id(cell->name), log_id(cell->type), log_id(module->name)); if (!port_wire->port_input) continue; + if (conn.second.is_fully_const()) + continue; SigSpec O = module->addWire(NEW_ID, GetSize(conn.second)); for (int i = 0; i < GetSize(conn.second); i++) { -- cgit v1.2.3