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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-08 05:20:15 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-08 05:20:15 +0100 |
| commit | b04051a0e2f859c0d9f11109e8e05e9740438f9b (patch) | |
| tree | b37765bbea60c12c3813d4389d50ca0b67a7f5eb /passes | |
| parent | 4abc8e695ad0b3b11ae687d776856dd98b56101d (diff) | |
| download | yosys-b04051a0e2f859c0d9f11109e8e05e9740438f9b.tar.gz yosys-b04051a0e2f859c0d9f11109e8e05e9740438f9b.tar.bz2 yosys-b04051a0e2f859c0d9f11109e8e05e9740438f9b.zip | |
Fixed keep attribute on wires in opt_clean
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_clean.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 8e3691b34..2921c92d8 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -54,7 +54,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) for (auto &it : module->wires) { RTLIL::Wire *wire = it.second; - if (wire->port_output) { + if (wire->port_output || wire->get_bool_attribute("\\keep")) { std::set<RTLIL::Cell*> cell_list; RTLIL::SigSpec sig = RTLIL::SigSpec(wire); assign_map.apply(sig); |